Ralph Mason

According to our database1, Ralph Mason authored at least 28 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A sub-harmonic injection locking clock multiplier with FLL PVT calibrator.
Microelectron. J., 2020

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2020

2019
A High-Performance Low Complexity All-Digital Fractional Clock Multiplier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2015
Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
A novel Injection Locked Rotary Traveling Wave Oscillator.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A 14b threshold configurable dynamically latched comparator for SAR ADCs.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

2012
Complete SOC Transceiver in 0.18 µm CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking.
IEEE J. Solid State Circuits, 2012

Phase calibration techniques for injection-locking LO-path based phase-shifting phased-array architectures.
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012

2011
Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2008
Subsampling Architecture for Low Power Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 14-mW 2.4-GHz CMOS transceiver for short range wireless sensor applications.
Proceedings of the ESSCIRC 2008, 2008

2006
Quantization noise reduction using multiphase PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2004
An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 0.18 μm CMOS 900 MHz receiver front-end using RF Q-enhanced filters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Improving the acquisition time of a PLL-based, integer-N frequency synthesizer.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A dual edge-triggered phase-frequency detector architecture.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

RF, Q-enhanced bandpass filters in standard 0.18µm CMOS with direct digital tuning.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1999
Phase Measurements for Direct Conversion AM Radio Navigation.
J. Intell. Transp. Syst., 1999

Mixed Signal DFT at GHz Frequencies.
J. Electron. Test., 1999

Analog DFT Using an Undersampling Technique.
IEEE Des. Test Comput., 1999

A toolset for construction of hybrid intelligent forecasting systems: application for water demand prediction.
Artif. Intell. Eng., 1999

A VLSI Programmable Cellular Automata Array for Multiplication in GF (2<sup>n</sup>).
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

6.5 mW CMOS low noise amplifier at 1.9 GHz.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High speed V.32 trellis encoder/decoder implementation using FPGA.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Two Improved Algorithms and Hardware Implementations for Key Distribution Using Extended Programmable Cellular Automata.
Proceedings of the 14th Annual Computer Security Applications Conference (ACSAC 1998), 1998

1995
Mapping hierarchical neural networks to VLSI hardware.
Neural Networks, 1995


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