Changxuan Han

Orcid: 0009-0009-7386-2115

According to our database1, Changxuan Han authored at least 6 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2023
A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA.
IEEE J. Solid State Circuits, March, 2023

A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 71-to-86GHz, 20.4dBm $\mathbf{P}_{\mathbf{out}}$, 6.0dB NF Transceiver with Quadrature Direct-Modulated Transmitter and Reflection-Less Heterodyne Receiver in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022


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