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Chanheum Han

Orcid: 0009-0002-1344-8341

According to our database1, Chanheum Han authored at least 3 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of six.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A V<sub>M</sub>-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces.
[BibTeX]
[DOI]
Chanheum Han
,
Ki-Soo Lee
,
Jun-Cheol Lee
,
Joo-Hyung Chae
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies.
[BibTeX]
[DOI]
Chanheum Han
,
Ki-Soo Lee
,
Joo-Hyung Chae
IEEE J. Solid State Circuits, May, 2025

2024
13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency.
[BibTeX]
[DOI]
Chanheum Han
,
Ki-Soo Lee
,
Joo-Hyung Chae
Proceedings of the IEEE International Solid-State Circuits Conference, 2024


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