Chanheum Han

According to our database, Chanheum Han authored at least 5 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

DPIM: A 2T1C eDRAM Transformer-in-Memory Chip With Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core.

Donghyuk Kim, Jae-Young Kim, Hyunjun Cho, Seungjae Yoo, Sukjin Lee, Sungwoong Yune, Sejeong Yang, Hoichang Jeong, Keonhee Park, Ki-Soo Lee, Jongchan Lee, Chanheum Han, Gunmo Koo, Yuli Han, Jaejin Kim, Jaemin Kim, Kyuho Jason Lee, Joo-Hyung Chae, Kunhee Cho, Joo-Young Kim

IEEE J. Solid State Circuits, May, 2026

37.6 A 0.092pJ/b and 7.7fJ/b/dB Cross-Self-Referenced Slope-Sampling Receiver with Long-Tail ISI Robustness for Next-Generation Low-Power Memory Interfaces.

Ki-Soo Lee, Chanheum Han, Joo-Hyung Chae

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

A V_M-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces.

Chanheum Han, Ki-Soo Lee, Jun-Cheol Lee, Joo-Hyung Chae

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies.

Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae

IEEE J. Solid State Circuits, May, 2025

2024

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency.

Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae

Proceedings of the IEEE International Solid-State Circuits Conference, 2024