Ki-Soo Lee
Orcid: 0009-0005-6019-5430
According to our database1,
Ki-Soo Lee authored at least 7 papers
between 2024 and 2026.
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Bibliography
2026
DPIM: A 2T1C eDRAM Transformer-in-Memory Chip With Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core.
IEEE J. Solid State Circuits, May, 2026
37.6 A 0.092pJ/b and 7.7fJ/b/dB Cross-Self-Referenced Slope-Sampling Receiver with Long-Tail ISI Robustness for Next-Generation Low-Power Memory Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
Sub 0.1-pJ/bit 14-Gb/s Receiver With Stack-Reduced Slicer Embedding One-Tap DFE for Low-Power Memory Interfaces.
IEEE Trans. Very Large Scale Integr. Syst., December, 2025
A V<sub>M</sub>-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025
25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies.
IEEE J. Solid State Circuits, May, 2025
A 0.9-V 15.6-Gb/s Single Ended NRZ Receiver with 1-Tap DFE for Low-Power Memory Interfaces.
Proceedings of the International Conference on Electronics, Information, and Communication, 2025
2024
13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024