Chao-Ching Hung

According to our database, Chao-Ching Hung authored at least 7 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2025

19.3 A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique.

Chao-Ching Hung, Chih-Hsien Shen, Chien-Li Lin, Mou Tzou, Kevin Fong, Yu-Li Hsueh

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2019

Toward Automotive Surround-View Radars.

Chih-Ming Hung, Alex T. C. Lin, B. C. Peng, Hua Wang, Jui-Lin Hsu, Yen-Ju Lu, Wei-Show Hsu, Jing-Hong Conan Zhan, Brian Juan, Chi-Hang Lok, Sam Lee, P. C. Hsiao, Qiang Zhou, Mark Wei, Hsiang-Yun Chu, Yu-Lun Chen, Chao-Ching Hung, Kevin Fong, Po-Chun Huang, Pierce Chen, Sheng-Yuan Su, Yan-Jiun Chen, Kehou Chen, Chun-Chao Tung, Yi-Jhan Hsieh, Tzung-Chuen Tsai, Yi-Fu Chen, Wei-Kuo Hsin, Liang Guo, Hanfei Liu, Dapeng Jin

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2011

A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm.

Chao-Ching Hung, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Noise Filtering Technique for Fractional-N Frequency Synthesizers.

Chao-Ching Hung, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2009

A Leakage-Compensated PLL in 65-nm CMOS Technology.

Chao-Ching Hung, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.

Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2009

A leakage-suppression technique for phase-locked systems in 65nm CMOS.

Chao-Ching Hung, Shen-Iuan Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2009