Lan-chou Cho

According to our database1, Lan-chou Cho authored at least 18 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 0.85mm<sup>2</sup> 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD<sub>2</sub> Self-Suppression and Pulling Mitigation.
IEEE J. Solid State Circuits, 2019

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits, 2017

2016
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits, 2016

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19psrms jitter and.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 0.27mm<sup>2</sup> 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC.
IEEE J. Solid State Circuits, 2011

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2009
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.
IEEE J. Solid State Circuits, 2009

2008
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology.
IEEE J. Solid State Circuits, 2007

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


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