Chihun Lee

According to our database1, Chihun Lee authored at least 8 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Scalable and High-Throughput Top-Down Manufacturing of Optical Metasurfaces.
Sensors, 2020

2012

2009
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.
IEEE J. Solid State Circuits, 2009

2008
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology.
IEEE J. Solid State Circuits, 2007

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


  Loading...