Chao-Liang Chen

According to our database, Chao-Liang Chen authored at least 4 papers between 1995 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

An auto-I/Q calibrated CMOS transceiver for 802.11g.

Yong-Hsiang Hsieh, Wei-Yi Hu, Shin-Ming Lin, Chao-Liang Chen, Wen-Kai Li, Sao-Jie Chen, David J. Chen

IEEE J. Solid State Circuits, 2005

A 6.25 mm² 2.4 GHz CMOS 802.11b Transceiver.

Yong-Hsiang Hsieh, Wei-Yi Hu, Wen-Kai Li, Shin-Ming Lin, Chao-Liang Chen, David J. Chen, Sao-Jie Chen

IEICE Trans. Electron., 2005

1999

A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.

Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1995

An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients.

Chao-Liang Chen, Kei-Yong Khoo, Alan N. Willson Jr.

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995