Alan N. Willson Jr.

Circuits Syst. Signal Process., 2019

2016

FIR Filter Design via Extended Optimal Factoring.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2016

Efficient Halfband FIR Filter Structures for RF and IF Data Converters.

[BibT_eX]

[DOI]

Ming Dai

IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015

Optimal Factoring of FIR Filters.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2015

Further Desensitized FIR Halfband Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

A 1-GHz direct digital frequency synthesizer in an FPGA.

[BibT_eX]

[DOI]

Matt Bergeron

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

2012

The Design of Hybrid Symmetric-FIR/Analog Pulse-Shaping Filters.

[BibT_eX]

[DOI]

Chia-Yu Yao

IEEE Trans. Signal Process., 2012

A 275 MHz quadrature modulator in 0.18-µm CMOS.

[BibT_eX]

[DOI]

Shilpa Agarwal

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A direct digital frequency synthesizer with minimized tuning latency of 12ns.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

Desensitized Half-Band Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 70dB SNDR 10-MHz BW hybrid delta-sigma/pipeline ADC in 0.18-µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A 1.2 Gb/s recursive polyphase cascaded integrator-comb prefilter for high speed digital decimation filters in 0.18-μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A low-supply PLL with Enhanced Cascode Compensation and a low-supply-sensitivity CCO.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Programmable 25-MHz to 6-GHz K<sub>vco</sub> Compensation.

[BibT_eX]

[DOI]

Jae Y. Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Frequency Synthesis with Arbitrary Input Clock Rate and Rational K/L Multiplier Ratio.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

The design of asymmetrical square-root pulse-shaping filters with wide eye-openings.

[BibT_eX]

[DOI]

Chia-Yu Yao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Enhanced delta-based layered decoding of WiMAX QC-LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation.

[BibT_eX]

[DOI]

Jae Y. Kim

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high-speed and high-accuracy interpolator for digital modems.

[BibT_eX]

[DOI]

Nicola Petra

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A flexible decoder IC for WiMAX QC-LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

The Design of Symmetric Square-Root Pulse-Shaping Filters for Transmitters and Receivers.

[BibT_eX]

[DOI]

Chia-Yu Yao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low-latency Memory-efficient 150-Mbps Turbo FEC Encoder and Decoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A two-stage angle-rotation architecture and its error analysis for efficient digital mixer implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Energy circulation quadrature LC-VCO.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Analysis and VLSI Realization of a Blind Beamforming Algorithm.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

Trigonometric polynomial interpolation for timing recovery.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Efficient VLSI implementation of N/N integer division.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Efficient hardware architectures for eigenvector and signal subspace estimation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

In Memoriam.

[BibT_eX]

[DOI]

Gabor C. Temes

Asad A. Abidi

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

An energy-efficient reconfigurable angle-rotator architecture.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On optimal IFIR filter design.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A new interpolated symbol timing recovery method.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An energy-efficient reconfigurable FFT/IFFT processor based on a multi-processor ring.

[BibT_eX]

[DOI]

Proceedings of the 2004 12th European Signal Processing Conference, 2004

A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data.

[BibT_eX]

[DOI]

Hiep T. Pham

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Optimal joint module-selection and retiming with carry-save representation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS.

[BibT_eX]

[DOI]

Arthur Torosyan

IEEE J. Solid State Circuits, 2003

A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-μm CMOS.

[BibT_eX]

[DOI]

David D. Hwang

IEEE J. Solid State Circuits, 2003

A 415 MHz direct digital quadrature modulator in 0.25-μm CMOS.

[BibT_eX]

[DOI]

Yanlin Wu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

The use of reduced two's-complement representation in low-power DSP design.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A ring-processor based blind beamformer design for use in wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A low power adaptive filter using dynamic reduced 2's-complement representation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Local stability analysis and hardware realization of an eigenvector tracking algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design of optimal hybrid form FIR filter.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multirate digital squarer architectures.

[BibT_eX]

[DOI]

Fengqi Yu

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Local stability analysis and systolic implementation of a subspace tracking algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits.

[BibT_eX]

[DOI]

Meng-Lin Yu

Proceedings of the 38th Design Automation Conference, 2001

2000

Analysis of conjugate gradient algorithms for adaptive filtering.

[BibT_eX]

[DOI]

Pi Sheng Chang

IEEE Trans. Signal Process., 2000

Motion-vector optimization of control grid interpolation and overlapped block motion compensation using iterated dynamic programming.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2000

A fast synchronizer for burst modems with simultaneous symbol timing and carrier phase estimations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Joint module selection and retiming with carry-save representation.

[BibT_eX]

[DOI]

Proceedings of the 10th European Signal Processing Conference, 2000

Efficient implementation of FIR filters using bit-level optimized carry-save additions.

[BibT_eX]

[DOI]

Proceedings of the 10th European Signal Processing Conference, 2000

The use of carry-save representation in joint module selection and retiming.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range.

[BibT_eX]

[DOI]

Avanindra Madisetti

IEEE J. Solid State Circuits, 1999

Hardware efficient architectures for coupled-form IIR filters.

[BibT_eX]

[DOI]

Fengqi Yu

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Improved-Booth encoding for low-power multipliers.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.

[BibT_eX]

[DOI]

Chao-Liang Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of an improved interpolation filter using a trigonometric polynomial.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Bit-level arithmetic optimization for carry-save additions.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

A variable-rate filtering system for digital communications.

[BibT_eX]

[DOI]

Larry A. Wasserman

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998

A new approach to the design of critically sampled M-channel uniform-band perfect-reconstruction linear-phase FIR filter banks.

[BibT_eX]

[DOI]

Parviz Saghizadeh

IEEE Trans. Signal Process., 1998

Rate-distortion optimal motion estimation algorithms for motion-compensated transform video coding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 1998

Low-power Viterbi decoder for CDMA mobile terminals.

[BibT_eX]

[DOI]

Inyup Kang

IEEE J. Solid State Circuits, 1998

A design method for half-band filters.

[BibT_eX]

[DOI]

Henry John Orchard

Proceedings of the 9th European Signal Processing Conference, 1998

1997

Application of filter sharpening to cascaded integrator-comb decimation filters.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1997

A Spatial and Temporal Motion Vector Coding Algorithm for Low-Bit-Rate Video Coding.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997

A flexible hardware-oriented fast algorithm for motion estimation.

[BibT_eX]

[DOI]

Fengqi Yu

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

A pipelined/interleaved IIR digital filter architecture.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Conjugate gradient method for adaptive direction-of-arrival estimation of coherent signals.

[BibT_eX]

[DOI]

Pi Sheng Chang

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996

A programmable FIR digital filter using CSD coefficients.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Design and optimization of a differentially coded variable block size motion compensation system.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

Cycle-Based Timing Simulations Using Event-Stream.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Rate-distortion optimal motion estimation algorithm for video coding.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Adaptive spectral estimation using the conjugate gradient algorithm.

[BibT_eX]

[DOI]

Pi Sheng Chang

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Motion vector optimization of control grid interpolation and overlapped block motion compensation using iterative dynamic programming.

[BibT_eX]

[DOI]

Proceedings of the 8th European Signal Processing Conference, 1996

1995

Design and implementation of efficient pipelined IIR digital filters.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1995

A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications.

[BibT_eX]

[DOI]

Avanindra Madisetti

IEEE Trans. Circuits Syst. Video Technol., 1995

An algorithm for identifying unstable operating points using SPICE.

[BibT_eX]

[DOI]

Michael M. Green

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Charge recovery on a databus.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Automated Programming of a Ring-Structured Multiprocessor Digital Filter IC.

[BibT_eX]

[DOI]

Michael J. Werter

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A High Accuracy Predictive Logarithmic Motion Estimation Algorithm for Video Coding.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients.

[BibT_eX]

[DOI]

Chao-Liang Chen

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A generic approach to the design of M-channel uniform-band perfect-reconstruction linear-phase FIR filter banks.

[BibT_eX]

[DOI]

Parviz Saghizadeh

Proceedings of the 1995 International Conference on Acoustics, 1995

Single-transistor transparent-latch clocking.

[BibT_eX]

[DOI]

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

An architecture for high-performance/small-area multipliers for use in digital filtering applications.

[BibT_eX]

[DOI]

Hing-Tsun Hung

IEEE J. Solid State Circuits, February, 1994

An improvement to the Powell and Chau linear phase IIR filters.

[BibT_eX]

[DOI]

Henry John Orchard

IEEE Trans. Signal Process., 1994

A New Approach to the Design of Three-Channel Perfect-Reconstruction Linear-Phase FIR Filter Banks.

[BibT_eX]

[DOI]

Parviz Saghizadeh

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Low Power CMOS Clock Buffer.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

High-Performance IIR QMF Banks for Speech Subband Coding.

[BibT_eX]

[DOI]

Abeer A. Alwan

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

An efficient 175 MHz programmable FIR digital filter.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

On the relationship between negatve differential resistance and stability for nonlinear one-ports.

[BibT_eX]

Michael M. Green

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

Lagrange multiplier approaches to the design of two-channel perfect-reconstruction linear-phase FIR filter banks.

[BibT_eX]

[DOI]

Bor-Rong Horng

IEEE Trans. Signal Process., 1992

A programmable digital filter IC employing multiple processors on a single chip.

[BibT_eX]

[DOI]

Michael J. Werter

IEEE Trans. Circuits Syst. Video Technol., 1992

1991

A theorem providing bounds on digital filter scaling factors.

[BibT_eX]

[DOI]

R. H. Brackert

Henry John Orchard

IEEE Trans. Signal Process., 1991

The design of low-complexity in linear-phase FIR filter banks using powers-of-two coefficients with an application to subband image coding.

[BibT_eX]

[DOI]

Bor-Rong Horng

Henry Samueli

IEEE Trans. Circuits Syst. Video Technol., 1991

1989

Design of an on-line multiply-add module for recursive digital filters.

[BibT_eX]

[DOI]

Ralph Hans Brackert Jr.

Milos D. Ercegovac

Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1970

New theorems on the equations of nonlinear DC transistor networks.

[BibT_eX]

[DOI]