Chen Nie

According to our database, Chen Nie authored at least 12 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Finite element method for a constant time delay subdiffusion equation with Riemann-Liouville fractional derivative.

Weiping Bu, Chen Nie, Weizhi Liao

CoRR, September, 2025

PICK: An SRAM-based Processing-in-Memory Accelerator for K-Nearest-Neighbor Search in Point Clouds.

Chen Nie, Chao Jiang, Liming Xiao, Weifeng Zhang, Zhezhi He

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration.

Jun Yan Lee, Chen Nie, Kang You, Yueyang Jia, Rui Yang, Zhezhi He

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations.

Chen Nie, Chenyu Tang, Jie Lin, Huan Hu, Chenyang Lv, Ting Cao, Weifeng Zhang, Li Jiang, Xiaoyao Liang, Weikang Qian, Yanan Sun, Zhezhi He

IEEE Trans. Computers, October, 2024

Social media use, social bot literacy, perceived threats from bots, and perceived bot control: a moderated-mediation model.

Wei Fang, Chen Nie

Behav. Inf. Technol., October, 2024

MASIM: An Efficient Multi-Array Scheduler for In-Memory SIMD Computation.

Xingyue Qian, Chen Nie, Zhezhi He, Weikang Qian

CoRR, 2024

SpikeZIP-TF: Conversion is All You Need for Transformer-based SNN.

Kang You, Zekai Xu, Chen Nie, Zhijie Deng, Qinghai Guo, Xiang Wang, Zhezhi He

Proceedings of the Forty-first International Conference on Machine Learning, 2024

PIMLC: Logic Compiler for Bit-Serial Based PIM.

Chenyu Tang, Chen Nie, Weikang Qian, Zhezhi He

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

GIM: Versatile GNN Acceleration with Reconfigurable Processing-in-Memory.

Chen Nie, Guoyang Chen, Weifeng Zhang, Zhezhi He

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph.

Chen Nie, Xianjue Cai, Chenyang Lv, Chen Huang, Weikang Qian, Zhezhi He

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System.

Chen Nie, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang, Zhezhi He

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2021

Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support.

Chen Nie, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, Zhezhi He

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021