Yanan Sun
Orcid: 0000-0001-8281-9121Affiliations:
- Shanghai Jiao Tong University, Shanghai, China
According to our database1,
Yanan Sun
authored at least 48 papers
between 2011 and 2024.
Collaborative distances:
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Bibliography
2024
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, February, 2024
2023
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
High Energy-Efficient Approximate In-SRAM Computing with Bit-Wise Compressor Configuration and Data-Aware Weight Remapping Method for Neural Network Acceleration.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification.
IEEE Trans. Geosci. Remote. Sens., 2022
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, 2021
An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit.
ACM Trans. Design Autom. Electr. Syst., 2018
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.
Microelectron. J., 2017
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.
Integr., 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the 26th International Conference on Microelectronics, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of the International SoC Design Conference, 2012
2011
Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011