Weikang Qian

Orcid: 0000-0002-5129-9431

According to our database1, Weikang Qian authored at least 102 papers between 2008 and 2024.

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Bibliography

2024
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits.
ACM Trans. Design Autom. Electr. Syst., January, 2024

2023
HEDALS: Highly Efficient Delay-Driven Approximate Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

GPT-LS: Generative Pre-Trained Transformer with Offline Reinforcement Learning for Logic Synthesis.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier With Unbiasedness and Configurability.
IEEE Trans. Computers, 2022

Joint Optimization of Randomizer and Computing Core for Low-Cost Stochastic Circuits.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

MinAC: Minimal-Area Approximate Compressor Design Based on Exact Synthesis for Approximate Multipliers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Quantified Satisfiability-based Simultaneous Selection of Multiple Local Approximate Changes under Maximum Error Bound.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Scheduling Information-Guided Efficient High-Level Synthesis Design Space Exploration.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Exploiting Uniform Spatial Distribution to Design Efficient Random Number Source for Stochastic Computing.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

ASPPLN: Accelerated Symbolic Probability Propagation in Logic Network.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space Exploration.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

Towards Low-Cost High-Accuracy Stochastic Computing Architecture for Univariate Functions: Design and Design Space Exploration.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

OPACT: Optimization of Approximate Compressor Tree for Approximate Multiplier.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SEALS: sensitivity-driven efficient approximate logic synthesis.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Write or not: programming scheme optimization for RRAM-based neuromorphic computing.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Linear Feedback Shift Register Reseeding for Stochastic Circuit Repairing and Minimization.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Approximate Logic Synthesis for FPGA by Decomposition.
Proceedings of the Approximate Computing, 2022

Approximate Multiplier Design for Energy Efficiency: From Circuit to Algorithm.
Proceedings of the Approximate Computing, 2022

2021
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths.
ACM J. Emerg. Technol. Comput. Syst., 2021

Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications.
IEEE Des. Test, 2021

Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?
Proceedings of the IEEE International Reliability Physics Symposium, 2021

MinSC: An Exact Synthesis-Based Method for Minimal-Area Stochastic Circuits under Relaxed Error Bound.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

DALTA: A Decomposition-based Approximate Lookup Table Architecture.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

GOMIL: Global Optimization of Multiplier by Integer Linear Programming.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
ALFANS: Multilevel Approximate Logic Synthesis Framework by Approximate Node Simplification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Introduction to special issue of 2019 China Semiconductor Technology International Conference (CSTIC) Symposium on Design and Automation of Circuits and Systems.
Integr., 2020

Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploring Target Function Approximation for Stochastic Circuit Minimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Optimally Approximated and Unbiased Floating-Point Multiplier with Runtime Configurability.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Accuracy Analysis for Stochastic Circuits with D Flip-Flop Insertion.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Reconfigurable Approximate Multiplier for Quantized CNN Applications.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders.
IEEE Trans. Computers, 2019

A high-accuracy approximate adder with correct sign calculation.
Integr., 2019

A Data Structure-Based Approximate Belief Propagation Decoder for Polar Codes.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Survey of Computation-Driven Data Encoding.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Area-Efficient Parallel Stochastic Computing with Shared Weighted Binary Generator.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit.
ACM Trans. Design Autom. Electr. Syst., 2018

A Graphical Model of Smoking-Induced Global Instability in Lung Cancer.
IEEE ACM Trans. Comput. Biol. Bioinform., 2018

Stochastic Circuit Synthesis by Cube Assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

The Promise and Challenge of Stochastic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Tier-Code: An XOR-Based RAID-6 Code with Improved Write and Degraded-Mode Read Performance.
Proceedings of the 2018 IEEE International Conference on Networking, 2018

Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Optimizing Stochastic Computing-Based FIR Filters.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

DALS: delay-driven approximate logic synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2018

Approximate Belief Propagation Decoder for Polar Codes.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Efficient batch statistical error estimation for iterative multi-level approximate logic synthesis.
Proceedings of the 55th Annual Design Automation Conference, 2018

A Branch-and-Bound-Based Minterm Assignment Algorithm for Synthesizing Stochastic Circuit.
Proceedings of the Advanced Logic Synthesis, 2018

2017
A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2017

An Accurate and Efficient Method to Calculate the Error Statistics of Block-based Approximate Adders.
CoRR, 2017

Approximate Disjoint Bi-Decomposition and Its Application to Approximate Logic Synthesis.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Design of accurate stochastic number generators with noisy emerging devices for stochastic computing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Approximate logic synthesis for FPGA by wire removal and local function change.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Learning Algorithm for Bayesian Networks and Its Efficient Implementation on GPUs.
IEEE Trans. Parallel Distributed Syst., 2016

Accelerating stochastic computation for binary classification applications.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

A General Sign Bit Error Correction Scheme for Approximate Adders.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Parallelizing FPGA Technology Mapping through Partitioning.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

An efficient method for multi-level approximate logic synthesis under error rate constraint.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Synthesizing cubes to satisfy a given intersection pattern.
Discret. Appl. Math., 2015

Timing-driven placement for carbon nanotube circuits.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

On microarchitectural modeling for CNFET-based circuits.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Minimizing Error of Stochastic Computation through Linear Transformation.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A general design of stochastic circuit and its synthesis.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A new approximate adder with low relative error and correct sign calculation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Computation on Stochastic Bit Streams Digital Image Processing Case Studies.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines.
IEEE Trans. Computers, 2014

BDD-based synthesis of reconfigurable single-electron transistor arrays.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Generating multiple correlated probabilities for MUX-based stochastic computing architecture.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Research of the Precision Clock Synchronization Based on IEEE 1588.
J. Softw., 2013

An ultra-fast parallel architecture using sequential circuits computing on random bits.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Optimizing multi-level combinational circuits for generating random bits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A Novel Learning Algorithm for Bayesian Network and Its Efficient Implementation on GPU
CoRR, 2012

Case Studies of Logical Computation on Stochastic Bit Streams.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An efficient implementation of numerical integration using logical computation on stochastic bit streams.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

The synthesis of linear Finite State Machine-based Stochastic Computational Elements.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Transforming Probabilities With Combinational Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

An Architecture for Fault-Tolerant Computation with Stochastic Logic.
IEEE Trans. Computers, 2011

Uniform approximation and Bernstein polynomials with coefficients in the unit interval.
Eur. J. Comb., 2011

2009
The Synthesis of Stochastic Circuits for Nanoscale Computation.
Int. J. Nanotechnol. Mol. Comput., 2009

The synthesis of combinational logic to generate probabilities.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A reconfigurable stochastic architecture for highly reliable computing.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
The synthesis of robust polynomial arithmetic with stochastic logic.
Proceedings of the 45th Design Automation Conference, 2008


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