Weifeng Zhang

Orcid: 0000-0002-4529-1679

Affiliations:
  • Alibaba Group, Sunnyvale, CA, USA
  • University of California, San Diego, CA, USA (PhD 2006)


According to our database1, Weifeng Zhang authored at least 20 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
A Classical Architecture For Digital Quantum Computers.
CoRR, 2023

GIM: Versatile GNN Acceleration with Reconfigurable Processing-in-Memory.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022
Towards Execution-Efficient LSTMs via Hardware-Guided Grow-and-Prune Paradigm.
IEEE Trans. Emerg. Top. Comput., 2022

N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2021
Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture.
IEEE Trans. Computers, 2021

EGEMM-TC: accelerating scientific computing on tensor cores with extended precision.
Proceedings of the PPoPP '21: 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2021

Enabling energy-efficient DNN training on hybrid GPU-FPGA accelerators.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

Simple Augmentation Goes a Long Way: ADRL for DNN Quantization.
Proceedings of the 9th International Conference on Learning Representations, 2021

PIM-DL: Boosting DNN Inference on Digital Processing In-Memory Architectures via Data Layout Optimizations.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Regularized Training and Tight Certification for Randomized Smoothed Classifier with Provable Robustness.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method.
ACM Trans. Design Autom. Electr. Syst., 2019

Sionnx: Automatic Unit Test Generator for ONNX Conformance.
CoRR, 2019

Software-Defined Design Space Exploration for an Efficient AI Accelerator Architecture.
CoRR, 2019

Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM.
CoRR, 2019

Parallel Training via Computation Graph Transformation.
Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019

2007
Accelerating and Adapting Precomputation Threads for Effcient Prefetching.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006
Speculative Code Value Specialization Using the Trace Cache Fill Unit.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

2005
An Event-Driven Multithreaded Dynamic Optimization Framework.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005


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