Chenggang Yan

Orcid: 0000-0001-5957-3207

Affiliations:
  • Nanjing University of Aeronautics and Astronautics, School of Electronic and Information Engineering, Nanjing, China
  • Southeast University, Nanjing, China (PhD 2020)


According to our database1, Chenggang Yan authored at least 22 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Design of High Hardware Efficiency Approximate Floating-Point FFT Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design of An Approximate FFT Processor Based on Approximate Complex Multipliers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique.
IEEE Trans. Circuits Syst., 2020

Active Noise Shaping SAR ADC Based on ISDM with the 5MHz Bandwidth.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A digital-mixing-based method for timing skew estimation in time-interleaved ADCs.
Microelectron. J., 2019

A low power wide tuning range two stage ring VCO with frequency enhancing.
IEICE Electron. Express, 2019

2018
A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control.
J. Circuits Syst. Comput., 2018


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