Chenglong Liang

Orcid: 0000-0001-8800-9920

According to our database1, Chenglong Liang authored at least 6 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 5.5-7.9 GHz Double Quadrature Cryo-CMOS Receiver Featuring a Wideband Noise Matching LNA for Quantum Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
Design of CMOS Integrated Circulator Based on Sequentially Switched Delay Lines With Body-Floating and Clock Boosting Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024

A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoM<sub>T</sub> in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2022
A Cap-Less High PSR and Low Output Noise Low-Dropout Regulator for Cryogenic Applications.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
A 0.025% DC Current Mismatch Charge Pump for PLL Applications.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 47K Noise Temperature CMOS S-band LNA for Cryogenic Applications.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021


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