Chi-Lun Tsai

According to our database1, Chi-Lun Tsai authored at least 2 papers between 2013 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2013
Variation-aware and adaptive-latency accesses for reliable low voltage caches.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013


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