Jinn-Shyan Wang
Orcid: 0000-0001-7638-0802
According to our database1,
Jinn-Shyan Wang
authored at least 114 papers
between 1995 and 2023.
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Bibliography
2023
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2020
Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
2017
Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the New Generation of CAS, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.
Integr., 2016
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs.
IEEE Trans. Multi Scale Comput. Syst., 2015
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.
IEEE J. Solid State Circuits, 2015
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET).
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm<sup>2</sup> all-digital delay-locked loop in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Comput. Networks, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology.
J. Circuits Syst. Comput., 2012
Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier.
IEICE Trans. Electron., 2012
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEICE Trans. Electron., 2011
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the International SoC Design Conference, 2011
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.
IEEE J. Solid State Circuits, 2010
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.
IEICE Trans. Electron., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism.
IEEE Trans. Circuits Syst. Video Technol., 2009
IEEE Trans. Circuits Syst. Video Technol., 2009
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices.
IEEE J. Solid State Circuits, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE J. Solid State Circuits, 2007
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. Video Technol., 2006
An AND-type match-line scheme for high-performance energy-efficient content addressable memories.
IEEE J. Solid State Circuits, 2006
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
2005
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.
IEEE Trans. Circuits Syst. Video Technol., 2005
IEEE J. Solid State Circuits, 2005
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
An all-digital 50% duty-cycle corrector.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
ACM Trans. Design Autom. Electr. Syst., 2003
IEEE J. Solid State Circuits, 2003
J. Inf. Sci. Eng., 2003
2002
IEEE J. Solid State Circuits, 2002
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques.
IEEE J. Solid State Circuits, 2002
J. Inf. Sci. Eng., 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE J. Solid State Circuits, 2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops.
IEEE J. Solid State Circuits, 2000
IEEE J. Solid State Circuits, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier.
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1995
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995