Chi-Pin Chen

According to our database, Chi-Pin Chen authored at least 3 papers between 2002 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.

Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.

Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2002

A new fast algorithms for mining association rules in large databases.

Cheng-Fa Tsai, Yi-Chau Lin, Chi-Pin Chen

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Yasmine Hammamet, Tunisia, October 6-9, 2002, 2002