Kwang-Jow Gan

According to our database1, Kwang-Jow Gan authored at least 13 papers between 2005 and 2013.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET.
Microelectronics Reliability, 2013

2011
Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process.
Microelectronics Journal, 2011

2010
Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources.
IEICE Transactions, 2010

Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit.
IEICE Transactions, 2010

2009
Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio.
IEICE Transactions, 2009

Multiple-Valued Memory Design by Standard BiCMOS Technique.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008
New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2006
The Design of MOS-NDR-Based Cellular Neural Network.
Proceedings of the International Joint Conference on Neural Networks, 2006

Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005


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