Chi Weon Yoon

According to our database, Chi Weon Yoon authored at least 4 papers between 2001 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

Low-power 3D graphics processors for mobile terminals.

Ju-Ho Sohn, Yong-Ha Park, Chi Weon Yoon, Ramchan Woo, Se-Jeong Park, Hoi-Jun Yoo

IEEE Commun. Mag., 2005

2002

A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.

Ramchan Woo, Chi Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo

IEEE J. Solid State Circuits, 2002

2001

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.

Chi Weon Yoon, Ramchan Woo, Jeengheon Kook, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yeo

IEEE J. Solid State Circuits, 2001

A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator.

Kangmin Lee, Chi Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Ja-Il Koo, Tae-Sung Jung, Hoi-Jun Yoo

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001