Hoi-Jun Yoo
Orcid: 0000-0002-6661-4879
According to our database1,
Hoi-Jun Yoo
authored at least 454 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2008, "For contributions to low-power and high-speed VLSI design".
Timeline
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On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.
IEEE J. Solid State Circuits, January, 2024
C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture.
IEEE J. Solid State Circuits, January, 2024
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing.
IEEE J. Solid State Circuits, January, 2024
A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing.
IEEE Micro, 2024
A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision.
CoRR, 2024
20.7 NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
20.8 Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
20.5 C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
LUTein: Dense-Sparse Bit-Slice Architecture With Radix-4 LUT-Based Slice-Tensor Processing Units.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit.
IEEE J. Solid State Circuits, October, 2023
Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks.
IEEE J. Solid State Circuits, October, 2023
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache.
IEEE J. Solid State Circuits, March, 2023
A Mobile 3-D Object Recognition Processor With Deep-Learning-Based Monocular Depth Estimation.
IEEE Micro, 2023
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC.
IEEE J. Solid State Circuits, 2023
A 709.3 TOPS/W Event-Driven Smart Vision SoC with High-Linearity and Reconfigurable MRAM PIM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
GPPU: A 330.4-μJ/ task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 15.9 mW 96.5 fps Memory-Efficient 3D Reconstruction Processor with Dilation-based TSDF Fusion and Block-Projection Cache System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Sibia: Signed Bit-slice Architecture for Dense DNN Acceleration with Slice-level Sparsity Exploitation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
A 3.8 mW 1.9 m Ω/√Hz Electrical Impedance Tomography Imaging with 28.4 M Ω High Input Impedance and Loading Calibration.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023
A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023
LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 33.6 FPS Embedding based Real-time Neural Rendering Accelerator with Switchable Computation Skipping Architecture on Edge Device.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-Precision.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 49.5 mW Multi-Scale Linear Quantized Online Learning Processor for Real-Time Adaptive Object Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Low-Power Graph Convolutional Network Processor With Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor.
IEEE Micro, 2022
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation.
IEEE Micro, 2022
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer.
IEEE J. Solid State Circuits, 2022
Design of Sub-10-μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing.
IEEE J. Solid State Circuits, 2022
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction.
IEEE J. Solid State Circuits, 2022
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction.
IEEE J. Solid State Circuits, 2022
FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems.
IEEE J. Solid State Circuits, 2022
CoRR, 2022
Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network.
CoRR, 2022
A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022
An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
A DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 0.82 μW CIS-Based Action Recognition SoC With Self-Adjustable Frame Resolution for Always-on IoT Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 64.1mW Accurate Real-Time Visual Object Tracking Processor With Spatial Early Stopping on Siamese Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Simultaneous Electrical Bio-Impedance Plethysmography at Different Body Parts: Continuous and Non-Invasive Monitoring of Pulse Wave Velocity.
IEEE Trans. Biomed. Circuits Syst., 2021
A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System.
IEEE J. Solid State Circuits, 2021
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection.
IEEE J. Solid State Circuits, 2021
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization.
IEEE J. Solid State Circuits, 2021
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation.
IEEE J. Solid State Circuits, 2021
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning.
IEEE J. Solid State Circuits, 2021
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching.
IEEE J. Solid State Circuits, 2021
An Overview of Sparsity Exploitation in CNNs for On-Device Intelligence With Software-Hardware Cross-Layer Optimizations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 3.6 TOPS/W Hybrid FP-FXP Deep Learning Processor with Outlier Compensation for Image-to-Image Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021
An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware Scheduling.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
A 1.15 TOPS/W Energy-Efficient Capsule Network Accelerator for Real-Time 3D Point Cloud Segmentation in Mobile Environment.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst., 2020
The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices.
IEEE Trans. Circuits Syst., 2020
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A 0.22-0.89 mW Low-Power and Highly-Secure Always-On Face Recognition Processor With Adversarial Attack Prevention.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation.
IEEE Trans. Circuits Syst., 2020
Proc. IEEE, 2020
IEEE J. Solid State Circuits, 2020
Wireless Body-Area-Network Transceiver and Low-Power Receiver With High Application Expandability.
IEEE J. Solid State Circuits, 2020
SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Extension of Direct Feedback Alignment to Convolutional and Recurrent Neural Network for Bio-plausible Deep Learning.
CoRR, 2020
Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 0.5V, 6.2μW, 0.059mm<sup>2</sup> Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
A 9.6 mW/Ch 10 MHz Wide-bandwidth Electrical Impedance Tomography IC with Accurate Phase Compensation for Breast Cancer Detection.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.8-V 82.9- $\mu$ W In-Ear BCI Controller IC With 8.8 PEF EEG Instrumentation Amplifier and Wireless BAN Transceiver.
IEEE J. Solid State Circuits, 2019
UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision.
IEEE J. Solid State Circuits, 2019
A Four-Camera VGA-Resolution Capsule Endoscope System With 80-Mb/s Body Channel Communication Transceiver and Sub-Centimeter Range Capsule Localization.
IEEE J. Solid State Circuits, 2019
CNNP-v2: A Memory-Centric Architecture for Low-Power CNN Processor on Domain-Specific Mobile Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
CoRR, 2019
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Intelligence on Silicon: From Deep-Neural-Network Accelerators to Brain Mimicking AI-SoCs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 5.37mW/Channel Pitch-Matched Ultrasound ASIC with Dynamic-Bit-Shared SAR ADC and 13.2V Charge-Recycling TX in Standard CMOS for Intracardiac Echocardiography.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 7.0fps Optical and Electrical Dual Tomographic Imaging SoC for Skin-Disease Diagnosis System.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
An Ultra-Low-Power Analog-Digital Hybrid CNN Face Recognition Processor Integrated with a CIS for Always-on Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-Time Image Segmentation on Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
93.8% Current Efficiency and 0.672 ns Transient Response Reconfigurable LDO for Wireless Sensor Network Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Direct Feedback Alignment Based Convolutional Neural Network Training for Low-Power Online Learning Processor.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Understanding Body Channel Communication : A review: from history to the future applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Analysis of Channel Characteristic for Body Channel Communication Transceiver Design.
Proceedings of the Body Area Networks. Smart IoT and Big Data for Intelligent Health Management, 2019
An 802.15.6 HBC Standard Compatible Transceiver and 90 pJ/b Full-Duplex Transceiver for Body Channel Communication.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
CNNP-v2: An Energy Efficient Memory-Centric Convolutional Neural Network Processor Architecture.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Guest Editorial Special Issue on Advances and Open Challenges for Integrated Circuits Detecting Bio Molecules.
IEEE Trans. Biomed. Circuits Syst., 2018
DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture.
IEEE Micro, 2018
IEEE J. Solid State Circuits, 2018
A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector.
IEEE J. Solid State Circuits, 2018
Low-Power Scalable 3-D Face Frontalization Processor for CNN-Based Face Recognition in Mobile Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
A 0.8V 82.9µW In-Ear BCI Controller System with 8.8 PEF EEG Instrumentational Amplifier and Wireless BAN Transceiver.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
B-Face: 0.2 MW CNN-Based Face Recognition Processor with Face Alignment for Mobile User Identification.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
4-Camera VGA-resolution capsule endoscope with 80Mb/s body-channel communication transceiver and Sub-cm range capsule localization.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.78 mW Low-Power 4.02 High-Compression Ratio Less than 10<sup>-6</sup> BER Error-Tolerant Lossless Image Compression Hardware for Wireless Capsule Endoscopy System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Energy-Efficient Speech-Extraction Processor for Robust User Speech Recognition in Mobile Head-Mounted Display Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Micro, 2017
A 502-GOPS and 0.984-mW Dual-Mode Intelligent ADAS SoC With Real-Time Semiglobal Matching and Intention Prediction for Smart Automotive Black Box System.
IEEE J. Solid State Circuits, 2017
A 1.4-m $\Omega$ -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
Sticker-Type Hybrid Photoplethysmogram Monitoring System Integrating CMOS IC With Organic Optical Sensors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 0.53mW ultra-low-power 3D face frontalization processor for face recognition with human-level accuracy in wearable devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A Real-Time and Energy-Efficient Embedded System for Intelligent ADAS with RNN-Based Deep Risk Prediction using Stereo Camera.
Proceedings of the Computer Vision Systems - 11th International Conference, 2017
A 24 μW 38.51 mΩrms resolution bio-impedance sensor with dual path instrumentation amplifier.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 274µW clock synchronized wireless body area network IC with super-regenerative RSSI for biomedical ad-hoc network system.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
An adaptive DC-balanced and multi-mode stimulator IC with 1GΩ output impedance for compact electro-acupuncture system.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017
Wearable 3D lung ventilation monitoring system with multi frequency electrical impedance tomography.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 0.5 V 54 µW Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 540-µW Duty Controlled RSSI With Current Reusing Technique for Human Body Communication.
IEEE Trans. Biomed. Circuits Syst., 2016
The effects of electrode impedance on receiver sensitivity in body channel communication.
Microelectron. J., 2016
An Energy-Efficient Embedded Deep Neural Network Processor for High Speed Visual Attention in Mobile Vision Recognition SoC.
IEEE J. Solid State Circuits, 2016
A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses.
IEEE J. Solid State Circuits, 2016
A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5µW 100 kb/s Super-Regenerative Transceiver for Body Channel Communication.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
14.2 A 502GOPS and 0.984mW dual-mode ADAS SoC with RNN-FIS engine for intention prediction in automotive black-box system.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robots.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
30-fps SNR equalized electrical impedance tomography IC with fast-settle filter and adaptive current control for lung monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A 43.7 mW 94 fps CMOS image sensor-based stereo matching accelerator with focal-plane rectification and analog census transformation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
An intelligent ADAS processor with real-time semi-global matching and intention prediction for 720p stereo vision.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
An 8.3mW 1.6Msamples/s multi-modal event-driven speech enhancement processor for robust speech recognition in smart glasses.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A fabric wrist patch sensor for continuous and comprehensive monitoring of the cardiovascular system.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Sticker-type ECG/PPG concurrent monitoring system hybrid integration of CMOS SoC and organic sensor device.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
An energy-efficient parallel multi-core ADAS processor with robust visual attention and workload-prediction DVFS for real-time HD stereo stream.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
A multimodal drowsiness monitoring ear-module system with closed-loop real-time alarm.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications.
IEEE Trans. Biomed. Circuits Syst., 2015
A Wearable EEG-HEG-HRV Multimodal System With Simultaneous Monitoring of tES for Mental Health Management.
IEEE Trans. Biomed. Circuits Syst., 2015
An Impedance and Multi-Wavelength Near-Infrared Spectroscopy IC for Non-Invasive Blood Glucose Estimation.
IEEE J. Solid State Circuits, 2015
A Vocabulary Forest Object Matching Processor With 2.07 M-Vector/s Throughput and 13.3 nJ/Vector Per-Vector Energy for Full-HD 60 fps Video Object Recognition.
IEEE J. Solid State Circuits, 2015
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications.
IEEE J. Solid State Circuits, 2015
A 4.9 mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System.
IEEE J. Solid State Circuits, 2015
A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung Ventilation Monitoring System.
IEEE J. Solid State Circuits, 2015
A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor.
IEEE J. Solid State Circuits, 2015
A 5.2 mW IEEE 802.15.6 HBC Standard Compatible Transceiver With Power Efficient Delay-Locked-Loop Based BPSK Demodulator.
IEEE J. Solid State Circuits, 2015
A 45 µW Injection-Locked FSK Wake-Up Receiver With Frequency-to-Envelope Conversion for Crystal-Less Wireless Body Area Network.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
A 4.84mW 30fps dual frequency division multiplexing electrical impedance tomography SoC for lung ventilation monitoring system.
Proceedings of the Symposium on VLSI Circuits, 2015
A 0.5-degree error 10mW CMOS image sensor-based gaze estimation processor with logarithmic processing.
Proceedings of the Symposium on VLSI Circuits, 2015
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
18.3 A 0.5V 54μW ultra-low-power recognition processor with 93.5% accuracy geometric vocabulary tree and 47.5% database compression.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
21.9 A wearable EEG-HEG-HRV multimodal system with real-time tES monitoring for mental health management.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
21.1 A 79pJ/b 80Mb/s full-duplex transceiver and a 42.5μW 100kb/s super-regenerative transceiver for body channel communication.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 3.13nJ/sample energy-efficient speech extraction processor for robust speech recognition in mobile head-mounted display systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 0.54-mW duty controlled RSSI with current reusing technique for human body communication.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 124.9fps memory-efficient hand segmentation processor for hand gesture in mobile devices.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Industrial Technology, 2015
A low-power and real-time augmented reality processor for the next generation smart glasses.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Intelligent Network-on-Chip With Online Reinforcement Learning for Portable HD Object Recognition Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Wearable Neuro-Feedback System With EEG-Based Mental Status Monitoring and Transcranial Electrical Stimulation.
IEEE Trans. Biomed. Circuits Syst., 2014
IEEE Micro, 2014
An 87-mA · min Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System.
IEEE J. Solid State Circuits, 2014
An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimation.
Proceedings of the Symposium on VLSI Circuits, 2014
A Vocabulary Forest-based object matching processor with 2.07M-vec/s throughput and 13.3nJ/vector energy in full-HD resolution.
Proceedings of the Symposium on VLSI Circuits, 2014
18.5 A 2.14mW EEG neuro-feedback processor with transcranial electrical stimulation for mental-health management.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
18.4 A 4.9mΩ-sensitivity mobile electrical impedance tomography IC for early breast-cancer detection system.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
An 1.92mW Feature Reuse Engine based on inter-frame similarity for low-power object recognition in video frames.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
3.8 mW electrocardiogram (ECG) filtered electrical impedance tomography IC using I/Q homodyne architecture for breast cancer diagnosis.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
An 1.61mW mixed-signal column processor for BRISK feature extraction in CMOS image sensor.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy AR.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
A 33μW/node Duty Cycle Controlled HBC Transceiver system for medical BAN with 64 sensor nodes.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Energy-efficient Mixed-mode support vector machine processor with analog Gaussian kernel.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2013
A 37.5 µW Body Channel Communication Wake-Up Receiver With Injection-Locking Ring Oscillator for Wireless Body Area Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Low Power and Self-Reconfigurable WBAN Controller for Continuous Bio-Signal Monitoring System.
IEEE Trans. Biomed. Circuits Syst., 2013
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams.
IEEE J. Solid State Circuits, 2013
A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2013
An 86 mW 98GOPS ANN-Searching Processor for Full-HD 30 fps Video Object Recognition With Zeroless Locality-Sensitive Hashing.
IEEE J. Solid State Circuits, 2013
An 87mA·min iontophoresis controller IC with dual-mode impedance sensor for patch-type transdermal drug delivery system.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 5.5mW IEEE-802.15.6 wireless body-area-network standard transceiver for multichannel electro-acupuncture application.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
1.2Gb/s 3.9pJ/b mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communication.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A multi-modal and tunable Radial-Basis-Funtion circuit with supply and temperature compensation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 34.1fps scale-space processor with two-dimensional cache for real-time object recognition.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 0.7pJ/bit 2Gbps self-synchronous serial link receiver using gated-ring oscillator for inductive coupling communication.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A high-throughput 16× super resolution processor for real-time object recognition SoC.
Proceedings of the ESSCIRC 2013, 2013
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
2012
A Sub-10 nA DC-Balanced Adaptive Stimulator IC With Multi-Modal Sensor for Compact Electro-Acupuncture Stimulation.
IEEE Trans. Biomed. Circuits Syst., 2012
IEEE Micro, 2012
A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine.
IEEE J. Solid State Circuits, 2012
A 75 µ W Real-Time Scalable Body Area Network Controller and a 25 µW ExG Sensor IC for Compact Sleep Monitoring Applications.
IEEE J. Solid State Circuits, 2012
A Low-Energy Crystal-Less Double-FSK Sensor Node Transceiver for Wireless Body-Area Network.
IEEE J. Solid State Circuits, 2012
A 0.24-nJ/b Wireless Body-Area-Network Transceiver With Scalable Double-FSK Modulation.
IEEE J. Solid State Circuits, 2012
Guest Editorial Emerging Circuits and Systems Techniques for Ultra-Low Power Body Sensor Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A sub-10nA DC-balanced adaptive stimulator IC with multimodal sensor for compact electro-acupuncture system.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 259.6μW nonlinear HRV-EEG chaos processor with body channel communication interface for mental health monitoring.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 2.1µW real-time reconfigurable wearable BAN controller with dual linked list structure.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 39 µW body channel communication wake-up receiver with injection-locking ring-oscillator for wireless body area network.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 86mW 98GOPS ANN-searching processor for Full-HD 30fps video object recognition with zeroless locality-sensitive hashing.
Proceedings of the 38th European Solid-State Circuit conference, 2012
The compact electro-acupuncture system for multi-modal feedback electro-acupuncture treatment.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Wearable mental-health monitoring platform with independent component analysis and nonlinear chaotic analysis.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A 46 μW motion artifact reduction bio-signal sensor with ICA based adaptive DC level control for sleep monitoring system.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Live demonstration: Wearable mental health monitoring system with planar-fashonable circuit board.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
2011
Proceedings of the Bio-Medical CMOS ICs, 2011
Proceedings of the Bio-Medical CMOS ICs, 2011
24-GOPS 4.5-mm<sup>2</sup> Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC.
IEEE Trans. Neural Networks, 2011
A Wirelessly Powered Electro-Acupuncture Based on Adaptive Pulsewidth Monophase Stimulation.
IEEE Trans. Biomed. Circuits Syst., 2011
IEEE J. Solid State Circuits, 2011
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition.
IEEE J. Solid State Circuits, 2011
A Low Energy Injection-Locked FSK Transceiver With Frequency-to-Amplitude Conversion for Body Sensor Applications.
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 75μW real-time scalable network controller and a 25μW ExG sensor IC for compact sleep-monitoring applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 0.24nJ/b wireless body-area-network transceiver with scalable double-FSK modulation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Fabric circuit board-based dry electrode and its characteristics for long-term physiological signal recording.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
The Smart Patches and Wearable Band (W-Band) for comfortable sleep monitoring system.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
A 92mW real-time traffic sign recognition system with robust light and dark adaptation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
An asynchronous mixed-mode neuro-fuzzy controller for energy efficient machine intelligence SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
ECG signal compression and classification algorithm with quad level vector for ECG holter system.
IEEE Trans. Inf. Technol. Biomed., 2010
Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.
IEEE Trans. Circuits Syst. Video Technol., 2010
Guest Editorial - Selected Papers From the 2010 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE Trans. Biomed. Circuits Syst., 2010
An attention controlled multi-core architecture for energy efficient object recognition.
Signal Process. Image Commun., 2010
Familiarity based unified visual attention model for fast and robust object recognition.
Pattern Recognit., 2010
A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 μ W Wirelessly Powered Sensor for a Continuous Health Monitoring System.
IEEE J. Solid State Circuits, 2010
A 0.5-μ V<sub>rms</sub> 12-μ W Wirelessly Powered Patch-Type Healthcare Sensor for Wearable Body Sensor Network.
IEEE J. Solid State Circuits, 2010
A Low-Energy Inductive Coupling Transceiver With Cm-Range 50-Mbps Data Communication in Mobile Device Applications.
IEEE J. Solid State Circuits, 2010
A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2010
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine.
IEEE J. Solid State Circuits, 2010
A 4.78 µs Dynamic Compensated Inductive Coupling Transceiver for Ubiquitous and Wearable Body Sensor Network.
IEICE Trans. Commun., 2010
Proceedings of the 4th International Conference on Pervasive Computing Technologies for Healthcare, 2010
Proceedings of the 14th IEEE International Symposium on Wearable Computers (ISWC 2010), 2010
Arm-band type textile-MP3 player with multi-layer Planar Fashionable Circuit Board (P-FCB) techniques.
Proceedings of the 14th IEEE International Symposium on Wearable Computers (ISWC 2010), 2010
A 3.9mW 25-electrode reconfigured thoracic impedance/ECG SoC with body-channel transponder.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A wirelessly-powered electro-acupuncture based on Adaptive Pulse Width Mono-Phase stimulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A lOMb/s 4ns jitter direct conversion low Modulation Index FSK demodulator for low-energy body sensor network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 30fps stereo matching processor based on belief propagation with disparity-parallel PE array architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A real-time compensated inductive transceiver for wearable MP3 player system on multi-layered planar fashionable circuit board.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Live demonstration: A real-time compensated inductive transceiver for wearable MP3 player system on multi-layered planar fashionable circuit board.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
A combined method to reduce motion artifact and power line interference for wearable healthcare systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
A 152-mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
A Wearable ECG Acquisition System With Compact Planar-Fashionable Circuit Board-Based Shirt.
IEEE Trans. Inf. Technol. Biomed., 2009
A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition.
IEEE Trans. Circuits Syst. Video Technol., 2009
A 200-Mbps 0.02-nJ/b Dual-Mode Inductive Coupling Transceiver for cm-Range Multimedia Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining.
IEEE Micro, 2009
A 1.12 pJ/b Inductive Transceiver With a Fault-Tolerant Network Switch for Multi-Layer Wearable Body Area Network Applications.
IEEE J. Solid State Circuits, 2009
Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08).
IEEE J. Solid State Circuits, 2009
An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC.
IEEE J. Solid State Circuits, 2009
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine.
IEEE J. Solid State Circuits, 2009
A 60 kb/s-10 Mb/s Adaptive Frequency Hopping Transceiver for Interference-Resilient Body Channel Communication.
IEEE J. Solid State Circuits, 2009
A 10.8 mW Body Channel Communication/MICS Dual-Band Transceiver for a Unified Body Sensor Network Controller.
IEEE J. Solid State Circuits, 2009
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor.
IET Comput. Digit. Tech., 2009
IEEE Computer Graphics and Applications, 2009
A wearable inductor channel design for blood pressure monitoring system in daily life.
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009
Proceedings of the 13th IEEE International Symposium on Wearable Computers (ISWC 2009), 2009
A 5.2mW self-configured wearable body sensor network controller and a 12µW 54.9% efficiency wirelessly powered sensor for continuous health monitoring system.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 10.8mW body-channel-communication/MICS dual-band transceiver for a unified body-sensor-network controller.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A 54GOPS 51.8mW analog-digital mixed mode Neural Perception Engine for fast object detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the Sixth International Workshop on Wearable and Implantable Body Sensor Networks, 2009
2008
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems.
IEEE Trans. Computers, 2008
A 195 mW, 9.1 MVertices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices.
IEEE J. Solid State Circuits, 2008
A 195 mW/152 mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
IEEE Commun. Mag., 2008
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 1.12mW Continuous Healthcare Monitor Chip Integrated on a Planar Fashionable Circuit Board.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 60kb/s-to-10Mb/s 0.37nJ/b Adaptive-Frequency-Hopping Transceiver for Body-Area Network.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 200Mbps 0.02nJ/b dual-mode inductive coupling transceiver for cm-range interconnection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the ESSCIRC 2008, 2008
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 3rd International ICST Conference on Body Area Networks, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the 4th International Workshop on Wearable and Implantable Body Sensor Networks, 2007
Proceedings of the 4th International Workshop on Wearable and Implantable Body Sensor Networks, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.
IEEE J. Solid State Circuits, 2006
Proceedings of the Tenth IEEE International Symposium on Wearable Computers (ISWC 2006), 2006
A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body.
Proceedings of the Tenth IEEE International Symposium on Wearable Computers (ISWC 2006), 2006
An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control.
Proceedings of the International Symposium on System-on-Chip, 2006
A 2Mb/s Wideband Pulse Transceiver with Direct-Coupled Interface for Human Body Communications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
A 10µW digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Development of a 3-D graphics rendering engine with lighting acceleration for handheld multimedia systems.
IEEE Trans. Consumer Electron., 2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
IEEE J. Solid State Circuits, 2005
IEEE Des. Test Comput., 2005
A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A 8-µW, 0.3-mm<sup>2</sup> RF-powered transponder with temperature sensor for wireless environmental monitoring.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
A 5.1-μW UHF RFID tag chip integrated with sensors for wireless environmental monitoring.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications.
IEEE J. Solid State Circuits, 2004
A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals.
IEEE J. Solid State Circuits, 2004
1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications.
IEEE J. Solid State Circuits, 2004
1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects.
IEEE J. Solid State Circuits, 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
SILENT: serialized low energy transmission coding for on-chip interconnection networks.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware 2004, 2004
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals.
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks.
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
IEEE J. Solid State Circuits, 2002
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth.
IEEE J. Solid State Circuits, 2002
Race logic architecture (RALA): a novel logic concept using the race scheme of input variables.
IEEE J. Solid State Circuits, 2002
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the Global Telecommunications Conference, 2002
2001
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system.
IEEE J. Solid State Circuits, 2001
A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification.
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1998
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F<sup>2</sup> cell [CMOS design].
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
1993
A Precision CMOS Voltage Reference with Enhanced Stability for the Application to Advance VLSIs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993