Ramchan Woo
According to our database1,
Ramchan Woo
authored at least 16 papers
between 2000 and 2010.
Collaborative distances:
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Bibliography
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2006
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications.
IEEE J. Solid State Circuits, 2006
2005
A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications.
IEEE J. Solid State Circuits, 2004
A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals.
IEEE J. Solid State Circuits, 2004
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware 2004, 2004
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals.
Proceedings of the ESSCIRC 2003, 2003
2002
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
IEEE J. Solid State Circuits, 2002
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth.
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.
IEEE J. Solid State Circuits, 2001
A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000