Chih-Wei Stanley Yeh

According to our database, Chih-Wei Stanley Yeh authored at least 2 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology.

Chih-Wei Stanley Yeh, S. Simon Wong

IEEE J. Solid State Circuits, 2015

2013

Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array.

Jiale Liang, Chih-Wei Stanley Yeh, S. Simon Wong, H.-S. Philip Wong

ACM J. Emerg. Technol. Comput. Syst., 2013