H.-S. Philip Wong

According to our database1, H.-S. Philip Wong authored at least 77 papers between 1995 and 2019.

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Bibliography

2019
The N3XT Approach to Energy-Efficient Abundant-Data Computing.
Proceedings of the IEEE, 2019

A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
J. Solid-State Circuits, 2018

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Coming Up N3XT, After 2D Scaling of Si CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Joint Source-Channel Coding with Neural Networks for Analog Data Compression and Storage.
Proceedings of the 2018 Data Compression Conference, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Resistive RAM-Centric Computing: Design and Modeling Methodology.
IEEE Trans. on Circuits and Systems, 2017

The End of Moore's Law: A New Beginning for Information Technology.
Computing in Science and Engineering, 2017

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

3D nanosystems enable embedded abundant-data computing: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies.
IEEE Trans. on Circuits and Systems, 2016

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Transforming nanodevices to next generation nanosystems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Neuromorphic architectures with electronic synapses.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Nano-engineered architectures for ultra-low power wireless body sensor nodes.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
IEEE Computer, 2015

Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Time-based sensor interface circuits in carbon nanotube technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RRAM based synaptic devices for neuromorphic visual systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Monolithic 3D integration: a path from concept to reality.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Layout optimization and template pattern verification for directed self-assembly (DSA).
Proceedings of the 52nd Annual Design Automation Conference, 2015

Contact pitch and location prediction for Directed Self-Assembly template verification.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Modeling and design optimization of ReRAM.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs.
J. Solid-State Circuits, 2014

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
JETC, 2014

Design considerations of synaptic device for neuromorphic computing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Design guidelines for 3D RRAM cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Video analytics using beyond CMOS devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Directed Self-Assembly (DSA) Template Pattern Verification.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Robust design and experimental demonstrations of carbon nanotube digital circuits.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Impact of III-V and Ge Devices on Circuit Performance.
IEEE Trans. VLSI Syst., 2013

Combinational Logic Design Using Six-Terminal NEM Relays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array.
JETC, 2013

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Carbon nanotube circuits: opportunities and challenges.
Proceedings of the Design, Automation and Test in Europe, 2013

Sacha: the Stanford carbon nanotube controlled handshaking robot.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Carbon Nanotube Robust Digital VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Metal-Oxide RRAM.
Proceedings of the IEEE, 2012

Interconnect scaling into the sub-10nm regime.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Phase Change Memory: Scaling and applications.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Circuit-aware device reliability criteria methodology.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Phase Change Memory.
Proceedings of the IEEE, 2010

Intel LVS logic as a combinational logic paradigm in CNT technology.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Efficient FPGAs using nanoelectromechanical relays.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Carbon nanotube circuits: Living with imperfections and variations.
Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010

Detachable nano-carbon chip with ultra low power.
Proceedings of the 47th Design Automation Conference, 2010

2009
Fabrication and Characterization of Emerging Nanoscale Memory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
Proceedings of the 46th Design Automation Conference, 2009

2008
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A Multi-Aperture Image Sensor With 0.7 µm Pixels in 0.11 µm CMOS Technology.
J. Solid-State Circuits, 2008

Carbon nanotube transistor compact model for circuit design and performance optimization.
JETC, 2008

A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
Device and Technology Challenges for Nanoscale CMOS.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Carbon nanotube transistor circuits: models and tools for design and performance optimization.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A 3D Multi-Aperture Image Sensor Architecture.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2002
Beyond the conventional transistor.
IBM Journal of Research and Development, 2002

High Performance Double-Gate Device Technology Challenges and Opportunities (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1998
Digital Imaging.
IEEE Micro, 1998

1995
CMOS scaling into the 21st century: 0.1 µm and beyond.
IBM Journal of Research and Development, 1995


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