H.-S. Philip Wong
Orcid: 0000-0002-0096-1472Affiliations:
- Stanford University, USA
According to our database1,
H.-S. Philip Wong
authored at least 121 papers
between 1995 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2001, "For contributions to solid-state image sensors and nanoscale CMOS devices.".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on id.loc.gov
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on d-nb.info
On csauthors.net:
Bibliography
2023
Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities.
Proc. IEEE, June, 2023
ACM Trans. Embed. Comput. Syst., 2023
Scaled contact length with low contact resistance in monolayer 2D channel transistors.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Neuromorph. Comput. Eng., December, 2022
Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi2Te3 Thermoelectric Interfacial Layer.
Dataset, May, 2022
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies.
CoRR, 2022
First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey Selectors.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (~3 MA/cm<sup>2</sup>) and Low Resistance Drift (~0.002 at 105°C).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the Device Research Conference, 2022
Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.
Proceedings of the Device Research Conference, 2022
2021
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor.
CoRR, 2021
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.
CoRR, 2021
2020
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver.
Proceedings of the International Conference on Neuromorphic Systems, 2020
2019
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019
Proceedings of the Device Research Conference, 2019
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
IEEE J. Solid State Circuits, 2018
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 76th Device Research Conference, 2018
The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology.
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 76th Device Research Conference, 2018
Joint Source-Channel Coding with Neural Networks for Analog Data Compression and Storage.
Proceedings of the 2018 Data Compression Conference, 2018
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Comput. Sci. Eng., 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
3D nanosystems enable <i>embedded</i> abundant-data computing: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays.
CoRR, 2016
Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses.
CoRR, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
2015
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures.
CoRR, 2015
Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Layout optimization and template pattern verification for directed self-assembly (DSA).
Proceedings of the 52nd Annual Design Automation Conference, 2015
Contact pitch and location prediction for Directed Self-Assembly template verification.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014
Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices.
CoRR, 2014
Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array.
CoRR, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array.
ACM J. Emerg. Technol. Comput. Syst., 2013
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE J. Solid State Circuits, 2008
Carbon nanotube transistor compact model for circuit design and performance optimization.
ACM J. Emerg. Technol. Comput. Syst., 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Carbon nanotube transistor circuits: models and tools for design and performance optimization.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2002
High Performance Double-Gate Device Technology Challenges and Opportunities (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
2001
Proc. IEEE, 2001
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