Chin-Fa Hsieh

According to our database, Chin-Fa Hsieh authored at least 10 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

High Performance Architecture of a Graphics Accelerator.

Chin-Fa Hsieh, Li-Chi Chen, Zhe-Hao Lin

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

Implementation of a Smart Checkout System Based on Face Recognition Using YOLO v3-tiny.

Chin-Fa Hsieh, Pin-Hong Liu, Jai-Xuan Lai, Shih-Hao Sun

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

Automatic Vehicle License Plate Recognition Based on YOLO v4 for Smart Parking Management System.

Chin-Fa Hsieh, Cheng-Zhi Lin, Zheng-Zhe Li, Cheng-Hsiu Cho

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2016

A SoC Integrating ADC and 2DDWT for Video/Image Processing.

Chin-Fa Hsieh, Tsung-Han Tsai, Shu-Chung Yi

IEICE Trans. Electron., 2016

2013

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design.

Mao-Hsu Yen, Chu Yu, Horng-Ru Liao, Chin-Fa Hsieh

VLSI Design, 2013

An arithmetic controller design for numerical control.

Shu-Chung Yi, Chin-Fa Hsieh

Comput. Electr. Eng., 2013

2008

A Novel Efficient VLSI Architecture of 2-D Discrete Wavelet Transform.

Chin-Fa Hsieh, Tsung-Han Tsai, Chih-Hung Lai, Tai-An Shan

Proceedings of the 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), 2008

2007

A Cost-Effective Noise-Reduction Filtering Structure Based on Unsymmetrical Working Windows.

Chin-Fa Hsieh, Tsung-Han Tsai, Shu-Ping Chang, Tai-An Shan

Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), 2007

2006

A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes.

Chin-Fa Hsieh, Tsung-Han Tsai, Neng-Jye Hsu, Chih-Hung Lai

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

The new architecture of radix-4 Chinese abacus adder.

Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006