Chun-Yu Lin
Orcid: 0000-0002-8885-7521Affiliations:
- National Taiwan University, Department of Electrical Engineering, Graduate Institute of Engineering, Taipei, Taiwan
- National Tsing Hua University, Hsinchu, Taiwan (former)
According to our database1,
Chun-Yu Lin authored at least 15 papers
between 2013 and 2026.
Collaborative distances:
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Bibliography
2026
A 185-μW, 40-MHz TCXO With a Differential-Pair-Based Polynomial Temperature Compensation Technique Achieving <±2.5 ppm Frequency Error.
IEEE J. Solid State Circuits, June, 2026
2025
A 0.01 mm<sup>2</sup> RC-Filter-Based Temperature Sensor with Phase-Domain DSM Readout Achieving 232fJ.K<sup>2</sup> Resolution FoM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025
2024
An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration.
IEEE J. Solid State Circuits, November, 2024
A 339-nW 32.768-kHz DFLL-Based Reference Clock Generator with an Embedded Temperature Sensor.
Proceedings of the 21st International SoC Design Conference, 2024
A 185-μW, ±2.5-ppm -40°C-80°C Analog TCXO With A Differential-Pair-Based Polynomial Temperature Compensation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2022
A Temperature-Compensated Crystal Oscillator With Piecewise Polynomial Varactor Compensation Achieving ±3.75-ppm Inaccuracy From -30°C to 90°C.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
29.5 A 0.008mm<sup>2</sup> 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
2019
A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2013
A 650-pJ/bit MedRadio Transmitter With an FIR-Embedded Phase Modulator for Medical Micro-Power Networks (MMNs).
IEEE Trans. Circuits Syst. I Regul. Pap., 2013