Chushin Afuso

According to our database, Chushin Afuso authored at least 7 papers between 1968 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1995

An Optimum Half-Hot Code Assignment Algorithm for Input Encoding and Its Application to Finite State Machines.

Yasunori Nagata, Masao Mukaidono, Chushin Afuso

IEICE Trans. Inf. Syst., 1995

1993

A Method of Test Pattern Generation for Multiple-Valued PLA's.

Yasunori Nagata, Chushin Afuso

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

1992

A universal literal circuit and its application to quaternary logic networks.

Chotei Zukeran, Yasunori Nagata, Chushin Afuso, Makoto Honda, Yutaka Nagamine

Syst. Comput. Jpn., 1992

1990

A State Assignment for p-Valued Sequential Machines.

Yasunori Nagata, Chotei Zukeran, Chushin Afuso

Syst. Comput. Jpn., 1990

1987

Design of micropower CMOS quaternary memory circuits.

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1987

1986

Design of low-power quaternary CMOS logic circuits.

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1986

1968

Analog Computation With Random Pulse Sequences

Chushin Afuso

PhD thesis, 1968