Clarence S. P. Lee

According to our database, Clarence S. P. Lee authored at least 2 papers between 2006 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays.

Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton

Int. J. Reconfigurable Comput., 2008

2006

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.

Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006