Scott Y. L. Chin

According to our database1, Scott Y. L. Chin authored at least 9 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation.
ACM Trans. Embedded Comput. Syst., 2012

2011
Towards scalable FPGA CAD through architecture.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2009
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms.
TRETS, 2009

Improving the memory footprint and runtime scalability of FPGA CAD algorithms.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

An analytical model relating FPGA architecture and place and route runtime.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Field-Programmable Gate Array Architectures.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays.
Int. J. Reconfig. Comp., 2008

2007
Memory Footprint Reduction for FPGA Routing Algorithms.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006
Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006


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