Steve Wilton

According to our database, Steve Wilton authored at least 172 papers between 1993 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Online Training from Streaming Data with Concept Drift on FPGAs.

Esther Roorda, Steven J. E. Wilton

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems.

Andrew David Gunter, Steven J. E. Wilton

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors.

Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Reformulating the FPGA Routability Prediction Problem with Machine Learning.

Andrew David Gunter, Steve Wilton

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems.

Andrew David Gunter, Steven J. E. Wilton

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

T-RecX: Tiny-Resource Efficient Convolutional neural networks with early-eXit.

Nikhil Pratap Ghanathe, Steve Wilton

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

FPGA Architecture Exploration for DNN Acceleration.

Esther Roorda, Seyedramin Rasoulinezhad, Philip H. W. Leong, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2022

Rethinking Embedded Blocks for Machine Learning Applications.

Seyedramin Rasoulinezhad, Esther Roorda, Steve Wilton, Philip H. W. Leong, David Boland

ACM Trans. Reconfigurable Technol. Syst., 2022

Adaptive Clock Management of HLS-generated Circuits on FPGAs.

Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2022

Positive-Phase Temperature Scaling for Quantum-Assisted Boltzmann Machine Training.

Jose P. Pinilla, Steven J. E. Wilton

Proceedings of the SC22: International Conference for High Performance Computing, 2022

Boosting Domain-Specific Debug Through Inter-frame Compression.

Zakary Nafziger, Martin Chua, Daniel Holanda Noronha, Steven J. E. Wilton

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

In-circuit tuning of deep learning designs.

Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk

J. Syst. Archit., 2021

MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications.

Nikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma, Steve Wilton, Aayan Kumar

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs.

Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays.

Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2020

Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs.

Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk

Proceedings of the International Conference on Field-Programmable Technology, 2020

Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs.

Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Layout-Aware Embedding for Quantum Annealing Processors.

Jose P. Pinilla, Steven J. E. Wilton

Proceedings of the High Performance Computing - 34th International Conference, 2019

An Overlay for Rapid FPGA Debug of Machine Learning Applications.

Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton

Proceedings of the International Conference on Field-Programmable Technology, 2019

Towards In-Circuit Tuning of Deep Learning Designs.

Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk

Proceedings of the International Conference on Computer-Aided Design, 2019

On-chip FPGA Debug Instrumentation for Machine Learning Applications.

Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Introduction to the Special Section on Deep Learning in FPGAs.

Deming Chen, Andrew Putnam, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2018

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug.

Fatemeh Eslami, Steven J. E. Wilton

ACM Trans. Design Autom. Electr. Syst., 2018

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks.

Daniel H. Noronha, Bahar Salehpour, Steven J. E. Wilton

CoRR, 2018

Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks.

Daniel Holanda Noronha, Philip Heng Wai Leong, Steven J. E. Wilton

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs.

Daniel Holanda Noronha, Kahlan Gibson, Bahar Salehpour, Steven J. E. Wilton

Proceedings of the International Conference on Field-Programmable Technology, 2018

Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques.

Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong

Proceedings of the International Conference on Field-Programmable Technology, 2018

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug.

Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Architecture Exploration for HLS-Oriented FPGA Debug Overlays.

Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Extending post-silicon coverage measurement using time-multiplexed FPGA overlays.

Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits.

Jeffrey Goeders, Steven J. E. Wilton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Rapid circuit-specific inlining tuning for FPGA high-level synthesis.

Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.

Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating.

Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug.

Fatemeh Eslami, Steven J. E. Wilton

SIGARCH Comput. Archit. News, 2016

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges.

Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton

CoRR, 2016

RAW Introduction and Committees.

Marco D. Santambrogio, Ramachandran Vaidyanathan, Diana Goehringer, Steven J. E. Wilton

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs.

Jose P. Pinilla, Steven J. E. Wilton

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Quantifying observability for in-system debug of high-level synthesis circuits.

Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Systems-on-Chip on FPGAs.

Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton

Proceedings of the FPGAs for Software Programmers, 2016

2015

Allowing Software Developers to Debug HLS Hardware.

Jeffrey B. Goeders, Steven J. E. Wilton

CoRR, 2015

RAW Introduction and Committees.

Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs.

Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

An adaptive virtual overlay for fast trigger insertion for FPGA debug.

Fatemeh Eslami, Steven J. E. Wilton

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs.

Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Hierarchical Dynamic Power-Gating in FPGAs.

Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

Incremental Trace-Buffer Insertion for FPGA Debug.

Eddie Hung, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2014

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network.

Eddie Hung, Steven J. E. Wilton

ACM Trans. Design Autom. Electr. Syst., 2014

Power Aware Architecture Exploration for Field Programmable Gate Arrays.

Jeffrey B. Goeders, Steven J. E. Wilton

J. Low Power Electron., 2014

A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices.

Assem A. M. Bsoul, Steven J. E. Wilton

J. Low Power Electron., 2014

Effective FPGA debug for high-level synthesis generated circuits.

Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Incremental distributed trigger insertion for efficient FPGA debug.

Fatemeh Eslami, Steven J. E. Wilton

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs.

Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry.

Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

Scalable Signal Selection for Post-Silicon Debug.

Eddie Hung, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2013

Towards development of an analytical model relating FPGA architecture parameters to routability.

Joydip Das, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2013

Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs.

Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton

IEEE Trans. Computers, 2013

Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics.

Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton

IEEE Des. Test, 2013

Maximum flow algorithms for maximum observability during FPGA debug.

Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers.

Eddie Hung, Steven J. E. Wilton

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices.

Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012

Optimizing Floating Point Units in Hybrid FPGAs.

Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2012

Formal-Analysis-Based Trace Computation for Post-Silicon Debug.

Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang

IEEE Trans. Very Large Scale Integr. Syst., 2012

Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation.

Cindy Mark, Scott Y. L. Chin, Lesley Shannon, Steven J. E. Wilton

ACM Trans. Embed. Comput. Syst., 2012

Multi-objective voltage island floorplanning using sequence pair representation.

Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov

Sustain. Comput. Informatics Syst., 2012

Emulation in post-silicon validation: It's not just for functionality anymore.

Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Rapid RTL-based signal ranking for FPGA prototyping.

Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

VersaPower: Power estimation for diverse FPGA architectures.

Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

An FPGA with power-gated switch blocks.

Assem A. M. Bsoul, Steven J. E. Wilton

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Limitations of incremental signal-tracing for FPGA debug.

Eddie Hung, Steven J. E. Wilton

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs.

Assem A. M. Bsoul, Steven J. E. Wilton

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Advances in 3D design and optimization.

Steven J. E. Wilton, Visvesh S. Sathe

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

An Analytical Model Relating FPGA Architecture to Logic Density and Depth.

Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk

IEEE Trans. Very Large Scale Integr. Syst., 2011

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs).

Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2011

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition.

Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

On evaluating signal selection algorithms for post-silicon debug.

Eddie Hung, Steven J. E. Wilton

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Sequence pair based voltage island floorplanning.

Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Accelerated FPGA architecture design: Capabilities and limitations of analytical models.

Joydip Das, Steven J. E. Wilton

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Speculative Debug Insertion for FPGAs.

Eddie Hung, Steven J. E. Wilton

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An analytical model relating FPGA architecture parameters to routability.

Joydip Das, Steven J. E. Wilton

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Towards scalable FPGA CAD through architecture.

Scott Y. L. Chin, Steven J. E. Wilton

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm.

Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Accelerating trace computation in post-silicon debug.

Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

An FPGA architecture supporting dynamically controlled power gating.

Assem A. M. Bsoul, Steven J. E. Wilton

Proceedings of the International Conference on Field-Programmable Technology, 2010

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).

Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Towards Analytical Methods for FPGA Architecture Investigation.

Steven J. E. Wilton

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces.

Bradley R. Quinton, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2009

Floating-Point FPGA: Architecture and Modeling.

Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2009

Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms.

Scott Y. L. Chin, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2009

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT.

Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms.

Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design.

Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

A detailed delay path model for FPGAs.

Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Modeling post-techmapping and post-clustering FPGA circuit depth.

Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Improving the memory footprint and runtime scalability of FPGA CAD algorithms.

Scott Y. L. Chin, Steven J. E. Wilton

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

An analytical model relating FPGA architecture and place and route runtime.

Scott Y. L. Chin, Steven J. E. Wilton

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.

Alastair M. Smith, Steven J. E. Wilton, Joydip Das

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Charge-borrowing decap: A novel circuit for removal of local supply noise violations.

Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Field-Programmable Gate Array Architectures.

Steven J. E. Wilton, Nathalie Chan King Choy, Scott Y. L. Chin, Kara K. W. Poon

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Practical Asynchronous Interconnect Network Design.

Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2008

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.

Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.

Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk

ACM Trans. Reconfigurable Technol. Syst., 2008

On the trade-off between power and flexibility of FPGA clock networks.

Julien Lamoureux, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2008

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units.

Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk

Int. J. Reconfigurable Comput., 2008

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays.

Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton

Int. J. Reconfigurable Comput., 2008

BackSpace: Moving Towards Reality.

Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton

Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Optimizing coarse-grained units in floating point hybrid FPGA.

Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A system-level stochastic circuit generator for FPGA architecture evaluation.

Cindy Mark, Ava Shui, Steven J. E. Wilton

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

An analytical model describing the relationships between logic architecture and FPGA density.

Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk

Proceedings of the FPL 2008, 2008

Rapid estimation of power consumption for hybrid FPGAs.

Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton

Proceedings of the FPL 2008, 2008

BackSpace: Formal Analysis for Post-Silicon Debug.

Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang

Proceedings of the Formal Methods in Computer-Aided Design, 2008

Session 14 - Advanced SoCs - techniques and applications.

Steven J. E. Wilton, Arif Rahman

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Memory Footprint Reduction for FPGA Routing Algorithms.

Scott Y. L. Chin, Steven J. E. Wilton

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Embedded Programmable Logic Core Enhancements for System Bus Interfaces.

Bradley R. Quinton, Steven J. E. Wilton

Proceedings of the FPL 2007, 2007

Clock-Aware Placement for FPGAs.

Julien Lamoureux, Steven J. E. Wilton

Proceedings of the FPL 2007, 2007

Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications.

Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton

Proceedings of the FPL 2007, 2007

A synthesizable datapath-oriented embedded FPGA fabric.

Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

GlitchLess: an active glitch minimization technique for FPGAs.

Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006

Product-Term-Based Synthesizable Embedded Programmable Logic Cores.

Andy Yan, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2006

System-on-Chip: Reuse and Integration.

Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov

Proc. IEEE, 2006

Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs.

Nathalie Chan King Choy, Steven J. E. Wilton

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Architecture and CAD for FPGA Clock Networks.

Julien Lamoureux, Steven J. E. Wilton

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Activity Estimation for Field-Programmable Gate Arrays.

Julien Lamoureux, Steven J. E. Wilton

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.

Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA clock network architecture: flexibility vs. area and power.

Julien Lamoureux, Steven J. E. Wilton

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.

Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

A novel FPGA architecture supporting wide, shallow memories.

Steven W. Oldridge, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2005

Routing architecture optimizations for high-density embedded programmable IP cores.

Peter Hallschmid, Steven J. E. Wilton

IEEE Trans. Very Large Scale Integr. Syst., 2005

A detailed power model for field-programmable gate arrays.

Kara K. W. Poon, Steven J. E. Wilton, Andy Yan

ACM Trans. Design Autom. Electr. Syst., 2005

Design considerations for soft embedded programmable logic cores.

Steven J. E. Wilton, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken'Ova, Resve Saleh

IEEE J. Solid State Circuits, 2005

On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays.

Julien Lamoureux, Steven J. E. Wilton

J. Low Power Electron., 2005

Challenges and opportunities for low power FPGAs in nanometer technologies.

Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Concentrator access networks for programmable logic cores on SoCs.

Bradley R. Quinton, Steven J. E. Wilton

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow.

Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Post-Silicon Debug Using Programmable Logic Cores.

Bradley R. Quinton, Steven J. E. Wilton

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Dynamic Voltage Scaling for Commercial FPGAs.

Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture.

Zion S. Kwok, Steven J. E. Wilton

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Advances in programmable logic.

Steven J. E. Wilton, Albert Stritter

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array.

Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Placement and routing for non-rectangular embedded programmable logic cores in SoC design.

Tony Wong, Steven J. E. Wilton

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays.

Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays.

Steven J. E. Wilton, Su-Shin Ang, Wayne Luk

Proceedings of the Field Programmable Logic and Application, 2004

Sequential synthesizable embedded programmable logic cores for system-on-chip.

Andy Yan, Steven J. E. Wilton

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

On the Interaction Between Power-Aware FPGA CAD Algorithms.

Julien Lamoureux, Steven J. E. Wilton

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Placement and routing for FPGA architectures supporting wide shallow memories.

Steven W. Oldridge, Steven J. E. Wilton

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Architectures and algorithms for synthesizable embedded programmable logic cores.

Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

SoC implementation issues for synthesizable embedded programmable logic cores.

James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Implementing logic in FPGA memory arrays: heterogeneous memory architectures.

Steven J. E. Wilton

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Sensitivity of FPGA power evaluation.

Kara K. W. Poon, Steven J. E. Wilton

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

A Flexible Power Model for FPGAs.

Kara K. W. Poon, Andy Yan, Steven J. E. Wilton

Proceedings of the Field-Programmable Logic and Applications, 2002

On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques.

Andy Yan, Rebecca Cheng, Steven J. E. Wilton

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

The architecture of dual-mode FPGA embedded system blocks.

Ernie Lin, Steven J. E. Wilton

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Structural analysis and generation of synthetic digital circuits with memory.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Very Large Scale Integr. Syst., 2001

Macrocell Architectures for Product Term Embedded Memory Arrays.

Ernie Lin, Steven J. E. Wilton

Proceedings of the Field-Programmable Logic and Applications, 2001

A crosstalk-aware timing-driven router for FPGAs.

Steven J. E. Wilton

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Detailed routing architectures for embedded programmable logic IP cores.

Peter Hallschmid, Steven J. E. Wilton

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Programmable logic IP cores in SoC design: opportunities and challenges.

Steven J. E. Wilton, Resve Saleh

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays.

Steven J. E. Wilton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

FPGA Implementation of a Prototype WDM On-Line Scheduler.

Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh

Proceedings of the Field-Programmable Logic and Applications, 2000

Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays.

Steven J. E. Wilton

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Architecture of cluster-based FPGAs with memory.

Jason P. Clifford, Steven J. E. Wilton

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

The memory/logic interface in FPGAs with large embedded memory arrays.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Very Large Scale Integr. Syst., 1999

A New Switch Block for Segmented FPGAs.

M. Imran Masud, Steven J. E. Wilton

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays.

William K. C. Ho, Steven J. E. Wilton

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998

SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays.

Steven J. E. Wilton

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Implementing logic in FPGA embedded memory arrays: architectural implications.

Steven J. E. Wilton

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996

CACTI: an enhanced cache access and cycle time model.

Steven J. E. Wilton, Norman P. Jouppi

IEEE J. Solid State Circuits, 1996

1995

Architecture of Centralized Field-Configurable Memory.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Tradeoffs in Two-Level On-Chip Caching.

Norman P. Jouppi, Steven J. E. Wilton

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993

Architectural Support for Block Transfers in a Shared-Memory Multiprocessor.

Steven J. E. Wilton, Zvonko G. Vranesic

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.

Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993