Clay S. Gloster Jr.

According to our database1, Clay S. Gloster Jr. authored at least 38 papers between 1988 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2021
A Multi-Memory Field-Programmable Custom Computing Machine for Accelerating Compute-Intensive Applications.
Proceedings of the 12th IEEE Annual Ubiquitous Computing, 2021

A mobile educational platform based on peer influence and instructional scaffolding for engaging students in out-of-class activities.
Proceedings of the 21st International Conference on Advanced Learning Technologies, 2021

2020
An FPGA-based Optimized Memory Controller for Accessing Multiple Memories.
Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020

An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAs.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Using Machine Learning to Estimate Utilization and Throughput for OpenCL-Based Matrix-Vector Multiplication (MVM).
Proceedings of the 10th Annual Computing and Communication Workshop and Conference, 2020

2019
A Remote Field-Programmable Custom Computing Machine Accelerator.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

2018
Building an Acceleration Overlay for Novice Students.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

MRS: Automated Assessment of Interactive Classroom Exercises.
Proceedings of the 49th ACM Technical Symposium on Computer Science Education, 2018

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive Applications.
Proceedings of the 37th IEEE International Performance Computing and Communications Conference, 2018

2017
A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System.
J. Circuits Syst. Comput., 2017

Improving the Accuracy of Arctan for Face Detection.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Smart City Service Acceleration on FPGAs.
Proceedings of the Third IEEE International Conference on Big Data Computing Service and Applications, 2017

2016
Dataflow to Hardware Synthesis Framework on FPGAs.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

Using Interactive Exercise in Mobile Devices to Support Evidence-based Teaching and Learning.
Proceedings of the 2016 ACM Conference on Innovation and Technology in Computer Science Education, 2016

Project based courses in control cyber physical system co-design.
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016

2015
Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Intelligent data mining and machine learning for mental health diagnosis using genetic algorithm.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

2014
Intelligent surveillance lifecycle architecture for epidemiological data clustering using Twitter and novel genetic algorithm.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2014

2013
Dynamic Disease Forecast Network Using Family Medical History.
Proceedings of the IEEE International Conference on Healthcare Informatics, 2013

2012
Intelligent teaching models for STEM related careers using a service-oriented architecture and management science.
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012

Intelligent optimization models for disease diagnosis using a service-oriented architecture and management science.
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012

2010
Prediction of inter-residue contact clusters from hydrophobic cores.
Int. J. Data Min. Bioinform., 2010

2009
Protein fold Classification with Genetic Algorithms and Feature Selection.
J. Bioinform. Comput. Biol., 2009

IRCDB: A Database of Inter-residues Contacts in Protein Chains.
Proceedings of the First International Conference on Advances in Databases, 2009

2007
A Configurable Processor Synthesis System.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
Optimizing the Design of a Configurable Digital Signal Processor for Accelerated Execution of the 2-D Discrete Cosine Transform.
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006

2000
Implementation of Multispectral Image Classification on a Remote Adaptive Computer.
VLSI Design, 2000

Parallel image processin gwith the block data paralel architecture.
IBM J. Res. Dev., 2000

1998
Implementation of a Probabilistic Neural Network for Multi-spectral Image Classification on an FPGA based Custom Computing Machine.
Proceedings of the 5th Brazilian Symposium on Neural Networks (SBRN '98), 1998

1996
Parallel image processing with the block data parallel architecture.
Proc. IEEE, 1996

1995
Partial scan selection for user-specified fault coverage.
Proceedings of the Proceedings EURO-DAC'95, 1995

1992
Cellular scan test generation for sequential circuits.
Proceedings of the conference on European design automation, 1992

1990
Built-in self-test with weighted random pattern hardware.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
Boundary scan with built-in self-test.
IEEE Des. Test, 1989

Hardware-Based Weighted Random Pattern Generation for Boundary Scan.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Boundary Scan with Cellular-Based Built-In Self-Test.
Proceedings of the Proceedings International Test Conference 1988, 1988


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