Franc Brglez

According to our database1, Franc Brglez authored at least 66 papers between 1981 and 2022.

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Bibliography

2022
Asymptotic Experiments with Data Structures: Bipartite Graph Matchings and Covers.
CoRR, 2022

2018
On Uncensored Mean First-Passage-Time Performance Experiments with Multiwalk in R<sup>p</sup>: a New Stochastic Optimization Algorithm.
CoRR, 2018

2017
Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve them.
Appl. Soft Comput., 2017

On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks.
Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

2014
Low-Autocorrelation Binary Sequences: on the Performance of Memetic-Tabu and Self-Avoiding Walk Solvers.
CoRR, 2014

2013
On Self-Avoiding Walks across n-Dimensional Dice and Combinatorial Optimization: An Introduction.
CoRR, 2013

2007
High-contrast algorithm behavior: observation, hypothesis, and experimental design.
Proceedings of the Workshop on Experimental Computer Science, 2007

Performance testing of combinatorial solvers with isomorph class instances.
Proceedings of the Workshop on Experimental Computer Science, 2007

2005
On SAT instance classes and a method for reliable performance experiments with SAT solvers.
Ann. Math. Artif. Intell., 2005

Effective bounding techniques for solving unate and binate covering problems.
Proceedings of the 42nd Design Automation Conference, 2005

2003
A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation.
Proceedings of the Theory and Applications of Satisfiability Testing, 2003

2001
Design of experiments and evaluation of BDD ordering heuristics.
Int. J. Softw. Tools Technol. Transf., 2001

Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization.
ACM J. Exp. Algorithmics, 2001

A Universal Client for Distributed Networked Design and Computing.
Proceedings of the 38th Design Automation Conference, 2001

2000
The Scientific Method and Design and Test.
IEEE Des. Test Comput., 2000

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Evaluating iterative improvement heuristics for bigraph crossing minimization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

User-configurable experimental design flows on the web: the ISCAS'99 experiments.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mirror, mirror, on the wall...is the new release any different at all? [BDDs].
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Equivalence classes of circuit mutants for experimental design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of experiments in CAD: context and new data sets for ISCAS'99.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Heuristics and Experimental Design for Bigraph Crossing Number Minimization.
Proceedings of the Algorithm Engineering and Experimentation, 1999

1998
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.
ACM Trans. Design Autom. Electr. Syst., 1998

WebWise Tcl/Tk: A Safe-Tcl/Tk-based Toolkit Enhanced for the World Wide Web.
Proceedings of the 6th Annual Tcl/Tk Conference, 1998

Design of experiments in BDD variable ordering: lessons learned.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
Proceedings of the 1998 Design, 1998

1997
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments.
Proceedings of GROUP'97, 1997

Executable Workflows: A Paradigm for Collaborative Design on the Internet.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Fast true delay estimation during high level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
Detectable perturbations: a paradigm for technology-specific multi-fault test generation.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Partial scan selection for user-specified fault coverage.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities.
SIGARCH Comput. Archit. News, 1994

Provably correct high-level timing analysis without path sensitization.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Functionality Fault Model: Feasibility and Applications.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions.
Proceedings of the Proceedings EURO-DAC'94, 1994

Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect.
Proceedings of the 31st Conference on Design Automation, 1994

Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications.
Proceedings of the 31st Conference on Design Automation, 1994

Clock Period Optimization During Resource Sharing and Assignment.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Transformations and resynthesis for testability of RT-level control-data path specifications.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema?
IEEE Des. Test Comput., 1993

Cost Minimization of Partitions into Multiple Devices.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
A framework and method for hierarchical test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Cellular scan test generation for sequential circuits.
Proceedings of the conference on European design automation, 1992

Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping.
Proceedings of the 29th Design Automation Conference, 1992

1991
Identification and Resynthesis of Pipelines in Sequential Networks.
Proceedings of the VLSI 91, 1991

Partitioning Sequential Circuits for Logic Optimization.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
OASIS: a silicon compiler for semi-custom design.
Proceedings of the First International Workshop on Rapid System Prototyping, 1990

Built-in self-test with weighted random pattern hardware.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Corolla Based Circuit Partitioning and Resynthesis.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Boundary scan with built-in self-test.
IEEE Des. Test, 1989

Hardware-Based Weighted Random Pattern Generation for Boundary Scan.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Boundary Scan with Cellular-Based Built-In Self-Test.
Proceedings of the Proceedings International Test Conference 1988, 1988

McMAP: a fast technology mapping procedure for multi-level logic synthesis.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

A modular scan-based testability system.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987
Testability-Driven Random Test-Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

Accelerated Transition Fault Simulation.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985
Fault Coverage Tools: Case Studies.
Proceedings of the Proceedings International Test Conference 1985, 1985

A Fast Fault Grader: Analysis and Applications.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing.
Proceedings of the Proceedings International Test Conference 1984, 1984

1981
Digital Signal Processing Considerations in Filter-Codec Testing.
Proceedings of the Proceedings International Test Conference 1981, 1981

A set of programs for MOS design.
Proceedings of the 18th Design Automation Conference, 1981


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