Cong Thuan Do

Orcid: 0000-0002-9950-1694

According to our database1, Cong Thuan Do authored at least 12 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Correction to: Aggressive GPU cache bypassing with monolithic 3D-based NoC.
J. Supercomput., April, 2023

Aggressive GPU cache bypassing with monolithic 3D-based NoC.
J. Supercomput., March, 2023

Deep Learning-based Prediction of Alertness and Drowsiness using EEG Signals.
Proceedings of the 12th International Symposium on Information and Communication Technology, 2023

2021
Enhancing Matrix Multiplication With a Monolithic 3-D-Based Scratchpad Memory.
IEEE Embed. Syst. Lett., 2021

2020
A novel warp scheduling scheme considering long-latency operations for high-performance GPUs.
J. Supercomput., 2020

2019
Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018
Application Characteristics-Aware Sporadic Cache Bypassing for high performance GPGPUs.
J. Parallel Distributed Comput., 2018

A Study on L1 Data Cache Bypassing Methods for High-Performance GPUs.
Proceedings of the Parallel and Distributed Computing, 2018

2017
Early miss prediction based periodic cache bypassing for high performance GPUs.
Microprocess. Microsystems, 2017

A dynamic CTA scheduling scheme for massive parallel computing.
Clust. Comput., 2017

2016
NTB branch predictor: dynamic branch predictor for high-performance embedded processors.
J. Supercomput., 2016

2015
A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines.
Microprocess. Microsystems, 2015


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