Young-Ho Gong

Orcid: 0000-0001-8270-7875

According to our database1, Young-Ho Gong authored at least 18 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory.
CoRR, 2024

Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Scale-CIM: Precision-scalable computing-in-memory for energy-efficient quantized neural networks.
J. Syst. Archit., 2023

Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 Caches.
IEEE Trans. Emerg. Top. Comput., 2021

Monolithic 3D stacked multiply-accumulate units.
Integr., 2021

Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks.
IEEE Embed. Syst. Lett., 2021

Characterizing the Thermal Feasibility of Monolithic 3D Microprocessors.
IEEE Access, 2021

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture.
IEEE Access, 2021

2019
Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018
Thermal Modeling and Validation of a Real-World Mobile AP.
IEEE Des. Test, 2018

2017
Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme.
Microprocess. Microsystems, 2017

An efficient trade-off between yield and energy for eDRAM caches under process variations.
Microprocess. Microsystems, 2017

Architecting large-scale SRAM arrays with monolithic 3D integration.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-Power Refresh.
IEEE Trans. Computers, 2016

Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches.
Microprocess. Microsystems, 2016

2013
Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay.
Proceedings of the International Symposium on Quality Electronic Design, 2013


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