Cristian Constantinescu

According to our database1, Cristian Constantinescu authored at least 23 papers between 1989 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
AMD EPYC™ 7002 Series - A Processor with Improved Soft Error Resilience.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

2014
Estimating the effect of single-event upsets on microprocessors.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2012
Error injection-based study of soft error propagation in AMD Bulldozer microprocessor module.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

2011
Introduction to the fifth workshop on dependable and secure nanocomputing.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

2010
Fourth workshop on dependable and secure nanocomputing.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

2009
Third workshop on dependable and secure nanocomputing.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

2008
Silent Data Corruption - Myth or reality?
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

Second workshop on dependable and secure nanocomputing.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2005
Dependability evaluation of a fault-tolerant processor by GSPN modeling.
IEEE Trans. Reliab., 2005

Dependability Benchmarking of Computing Systems - Panel Statement.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

Neutron SER Characterization of Microprocessors.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

2003
Experimental evaluation of error-detection mechanisms.
IEEE Trans. Reliab., 2003

Trends and Challenges in VLSI Circuit Reliability.
IEEE Micro, 2003

2002
Impact of Deep Submicron Technology on Dependability of VLSI Circuits.
Proceedings of the 2002 International Conference on Dependable Systems and Networks (DSN 2002), 2002

2001
Dependability Analysis of a Fault-Tolerant Processor.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

2000
Teraflops Supercomputer: Architecture and Validation of the Fault Tolerance Mechanisms.
IEEE Trans. Computers, 2000

1999
Using Physical and Simulated Fault Injection to Evaluate Error Detection Mechanisms.
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

Assessing Error Detection Coverage by Simulated Fault Injection.
Proceedings of the Dependable Computing, 1999

1998
Validation of the Fault/Error Handling Mechanisms of the Teraflops Supercomputer.
Proceedings of the Digest of Papers: FTCS-28, 1998

1990
A perfomability approach to the cost minimization of a class of gracefully degrading computer systems.
Microprocessing and Microprogramming, 1990

1989
Effect of transient faults on gracefully degrading processor arrays.
Microprocessing and Microprogramming, 1989

A Fault-Tolerant Microcomputer for Advanced Control: Architecture and Performability Analysis.
Proceedings of the Real-Time Systems Symposium, 1989

Microcomputer-Based, Gracefully Degrading Industrial Controller.
Proceedings of the Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 1989


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