Takashi Nanya
According to our database1,
Takashi Nanya
authored at least 93 papers
between 1978 and 2012.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2002, "For contribution to the theory and design of self-checking and asynchronous VLSI systems.".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2012
IEEE Secur. Priv., 2012
2011
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
2010
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Analysis of Inter-Module Error Propagation Paths in Monolithic Operating System Kernels.
Proceedings of the Eighth European Dependable Computing Conference, 2010
Pair and swap: An approach to graceful degradation for dependable chip multiprocessors.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
2009
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation.
IPSJ Trans. Syst. LSI Des. Methodol., 2009
An optimal lifetime-adaptive method for wireless sensor networks.
Comput. Syst. Sci. Eng., 2009
Zapmem: A Framework for Testing the Effect of Memory Corruption Errors on Operating System Kernel Reliability.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges.
Proceedings of the Service Availability, 5th International Service Availability Symposium, 2008
Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values.
Proceedings of the Workshops Proceedings of the 8th IEEE International Conference on Data Mining (ICDM 2008), 2008
Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation.
Proceedings of the Seventh European Dependable Computing Conference, 2008
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries.
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper).
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
An efficient cache replacement algorithm for multimedia object caching.
Comput. Syst. Sci. Eng., 2007
Comput. Commun., 2007
Proceedings of the Third International Conference on Semantics, 2007
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007
Topology Discovery in Dynamic and Decentralized Networks with Mobile Agents and Swarm Intelligence.
Proceedings of the Seventh International Conference on Intelligent Systems Design and Applications, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Power reduction of chip multi-processors using shared resource control cooperating with DVFS.
Proceedings of the 25th International Conference on Computer Design, 2007
An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks.
Proceedings of IEEE International Conference on Communications, 2007
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006
Proceedings of the Interdisciplinary and Multidisciplinary Research in Computer Science, 2006
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006
2005
Proceedings of the 2005 International Conference on Semantics, 2005
Proceedings of the 2005 International Conference on Semantics, 2005
2004
Proceedings of the 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the Grid and Cooperative Computing, Second International Workshop, 2003
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.
Proceedings of the 2003 Design, 2003
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
Logic optimization for asynchronous speed independent controllers using transduction method.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
High Throughput Asynchronous Domino Using Dual output Buffer.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Logic Optimization for Asynchronous SI Controllers using Transduction Method.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
2001
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs.
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000
1999
A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation.
IEEE Trans. Computers, 1999
1998
IEEE Trans. Computers, 1998
Syst. Comput. Jpn., 1998
Int. J. Netw. Manag., 1998
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design.
Proceedings of the ASP-DAC '98, 1998
1997
Syst. Comput. Jpn., 1997
Non-Broadcast Network Fault-Monitoring Based on System-Level Diagnosis.
Proceedings of the Integrated Network Management V, 1997
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
1996
Syst. Comput. Jpn., 1996
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Hierarchical Adaptive Distributed System-Level Diagnosis Applied for SNMP-based Network Fault Management.
Proceedings of the 15th Symposium on Reliable Distributed Systems, 1996
An SNMP-based implementation of the adaptive distributed system-level diagnosis algorithm for LAN fault management.
Proceedings of the 1996 Network Operations and Management Symposium, 1996
Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
Syst. Comput. Jpn., 1995
Syst. Comput. Jpn., 1995
Gracefully Degrading Systems Using the Bulk-Synchronous Parallel Model with Randomised Shared Memory.
Proceedings of the Digest of Papers: FTCS-25, 1995
Proceedings of the Digest of Papers: FTCS-25, 1995
1994
Syst. Comput. Jpn., 1994
IEEE Des. Test Comput., 1994
Timing-reliability evaluation of asynchronous circuits based on different delay models.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994
1992
Proceedings of the Digest of Papers: FTCS-22, 1992
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
A strongly fault-secure and strongly code-disjoint realization of combinational circuits.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989
1988
Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors.
IEEE Trans. Computers, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988
1987
Syst. Comput. Jpn., 1987
1986
1984
IEEE Trans. Computers, 1984
1983
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".
IEEE Trans. Computers, 1983
1979
IEEE Trans. Computers, 1979
1978
IEEE Trans. Computers, 1978