D. V. Poornaiah

According to our database, D. V. Poornaiah authored at least 3 papers between 1993 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1996

A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.

D. V. Poornaiah, P. V. Ananda Mohan

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.

D. V. Poornaiah, P. V. Ananda Mohan

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1993

Design and VLSI implementation of a novel concurrent 16-bit multiplier-accumulator for DSP applications.

D. V. Poornaiah, R. Haribabu, M. Omair Ahmad

Proceedings of the IEEE International Conference on Acoustics, 1993