Daher Kaiss

According to our database, Daher Kaiss authored at least 10 papers between 2001 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

Post-silicon timing diagnosis made simple using formal technology.

Daher Kaiss, Jonathan Kalechstain

Proceedings of the Formal Methods in Computer-Aided Design, 2014

2009

A compositional theory for post-reboot observational equivalence checking of hardware.

Zurab Khasidashvili, Daher Kaiss, Doron Bustan

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2007

Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.

Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006

Boolean Rings for Intersection-Based Satisfiability.

Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss

Proceedings of the Logic for Programming, 2006

Seqver : A Sequential Equivalence Verifier for Hardware Designs .

Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Post-reboot Equivalence and Compositional Verification of Hardware.

Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

2004

Boolean Ring Satisfiability.

Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss

Proceedings of the SAT 2004, 2004

Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.

Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2001

An enhanced cut-points algorithm in formal equivalence verification.

Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.

John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss

Proceedings of the Computer Aided Verification, 13th International Conference, 2001