Doron Bustan

According to our database1, Doron Bustan authored at least 11 papers between 2000 and 2012.

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Bibliography

2012
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience.
IEEE Des. Test Comput., 2012

2009
A compositional theory for post-reboot observational equivalence checking of hardware.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2006
Some Complexity Results for SystemVerilog Assertions.
Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005
Regular Vacuity.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
Applicability of fair simulation.
Inf. Comput., 2004

A Measured Collapse of the Modal µ-Calculus Alternation Hierarchy.
Proceedings of the STACS 2004, 2004

Verifying omega-Regular Properties of Markov Chains.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003
Simulation-based minimazation.
ACM Trans. Comput. Log., 2003

Resets vs. Aborts in Linear Temporal Logic.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2003

2002
Equivalence-based reductions and checking for preorders.
PhD thesis, 2002

2000
Simulation Based Minimization.
Proceedings of the Automated Deduction, 2000


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