Zurab Khasidashvili

Orcid: 0000-0001-9883-6997

According to our database1, Zurab Khasidashvili authored at least 55 papers between 1988 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
SMLP: Symbolic Machine Learning Prover.
CoRR, 2024

2022
Accelerating System-Level Debug Using Rule Learning and Subgroup Discovery Techniques.
CoRR, 2022

Combining Constraint Solving and Bayesian Techniques for System Optimization.
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

2021
Feature range analysis.
Int. J. Data Sci. Anal., 2021

Bayesian Optimisation with Formal Guarantees.
CoRR, 2021

2020
Selecting Stable Safe Configurations for Systems Modelled by Neural Networks with ReLU Activation.
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020

2019
Range Analysis and Applications to Root Causing.
Proceedings of the 2019 IEEE International Conference on Data Science and Advanced Analytics, 2019

2017
Symbolic trajectory evaluation for word-level verification: theory and implementation.
Formal Methods Syst. Des., 2017

2016
Predicate Elimination for Preprocessing in First-Order Theorem Proving.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

2015
EPR-based k-induction with Counterexample Guided Abstraction Refinement.
Proceedings of the Global Conference on Artificial Intelligence, 2015

Word-Level Symbolic Trajectory Evaluation.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014
From visual to logical formalisms for SoC validation.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

2012
Preprocessing techniques for first-order clausification.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

EPR-Based Bounded Model Checking at Word Level.
Proceedings of the Automated Reasoning - 6th International Joint Conference, 2012

2011
Implicative Simultaneous Satisfiability and Applications.
Proceedings of the Hardware and Software: Verification and Testing, 2011

2010
Encoding industrial hardware verification problems into effectively propositional logic.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009
Verifying equivalence of memories using a first order logic theorem prover.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

A compositional theory for post-reboot observational equivalence checking of hardware.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Assume-guarantee validation for STE properties within an SVA environment.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2008
On Formal Equivalence Verification of Hardware.
Proceedings of the Computer Science, 2008

2007
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
Seqver : A Sequential Equivalence Verifier for Hardware Designs .
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Post-reboot Equivalence and Compositional Verification of Hardware.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

2005
The conflict-free Reduction Geometry.
Theor. Comput. Sci., 2005

Encoding RTL Constructs for MathSAT: a Preliminary Report.
Proceedings of the Third Workshop on Pragmatics of Decision Procedures in Automated Reasoning, 2005

Simultaneous SAT-Based Model Checking of Safety Properties.
Proceedings of the Hardware and Software Verification and Testing, 2005

Expression Reduction Systems and Extensions: An Overview.
Proceedings of the Processes, 2005

2004
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
SAT-based methods for sequential hardware equivalence verification without synchronization.
Proceedings of the First International Workshop on Bounded Model Checking, 2003

An Abstract Concept of Optimal Implementation.
Proceedings of the 3rd International Workshop on Reduction Strategies in Rewriting and Programming, 2003

Stable Computational Semantics of Conflict-Free Rewrite Systems (Partial Orders with Duplication).
Proceedings of the Rewriting Techniques and Applications, 14th International Conference, 2003

2002
Relating conflict-free stable transition and event models via redex families.
Theor. Comput. Sci., 2002

An Abstract Böhm-normalization.
Proceedings of the 2nd International Workshop on Reduction Strategies in Rewriting and Programming, 2002

Static Analysis of Modularity of beta-Reduction in the Hyperbalanced lambda-Calculus.
Proceedings of the Rewriting Techniques and Applications, 13th International Conference, 2002

TRANS: efficient sequential verification of loop-free circuits.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
On the longest perpetual reductions in orthogonal expression reduction systems.
Theor. Comput. Sci., 2001

Perpetuality and Uniform Normalization in Orthogonal Rewrite Systems.
Inf. Comput., 2001

Uniform Normalisation beyond Orthogonality.
Proceedings of the Rewriting Techniques and Applications, 12th International Conference, 2001

An enhanced cut-points algorithm in formal equivalence verification.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000
A syntactical analysis of normalization.
J. Log. Comput., 2000

Stable results and relative normalization.
J. Log. Comput., 2000

1998
Normalization of Typable Terms by Superdevelopments.
Proceedings of the Computer Science Logic, 12th International Workshop, 1998

1997
Relating Conflict-Free Stable Transition and Event Models (Extended Abstract).
Proceedings of the Mathematical Foundations of Computer Science 1997, 1997

The Geometry of Orthogonal Reduction Spaces.
Proceedings of the Automata, Languages and Programming, 24th International Colloquium, 1997

Perpetuality and Uniform Normalization.
Proceedings of the Algebraic and Logic Programming, 6th International Joint Conference, 1997

1996
Minimal Relative Normalization in Orthogonal Expression Reduction Systems.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1996

Relative Normalization in Deterministic Residual Structures.
Proceedings of the Trees in Algebra and Programming, 1996

Discrete Normalization and Standardization in Deterministic Residual Structures.
Proceedings of the Algebraic and Logic Programming, 5th International Conference, 1996

1995
Context-sensitive conditional expression reduction systems.
Proceedings of the Joint COMPUGRAPH/SEMAGRAPH Workshop on Graph Rewriting and Computation, 1995

1994
Perpetuality and Strong Normalization in Orthogonal Term Rewriting Systems.
Proceedings of the STACS 94, 1994

Relative Normalization in Orthogonal Expression Reduction Systems.
Proceedings of the Conditional and Typed Rewriting Systems, 4th International Workshop, 1994

On Higher Order Recursive Program Schemes.
Proceedings of the Trees in Algebra and Programming, 1994

1993
Optimal Normalization in Orthogonal Term Rewriting Systems.
Proceedings of the Rewriting Techniques and Applications, 5th International Conference, 1993

On the Equivalence of Persistent Term Rewriting Systems and Recursive Program Schemes.
Proceedings of the Second Israel Symposium on Theory of Computing Systems, 1993

1988
beta-reductions and beta developments of lambda terms with the least number of steps.
Proceedings of the COLOG-88, 1988


  Loading...