Dariusz Kania

Orcid: 0000-0002-8748-4794

According to our database1, Dariusz Kania authored at least 37 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Switching Activity Reduction of SOP Networks.
IEEE Access, 2024

2023
Decomposition Approaches for Power Reduction.
IEEE Access, 2023

2022
A Music Classification Approach Based on the Trajectory of Fifths.
IEEE Access, 2022

2021
Technology Mapping for LUT-Based FPGA
Lecture Notes in Electrical Engineering 713, Springer, ISBN: 978-3-030-60487-5, 2021

Frequency Estimation in Interpolated Discrete Fourier Transform With Generalized Maximum Sidelobe Decay Windows for the Control of Power.
IEEE Trans. Ind. Informatics, 2021

Trajectory of Fifths in Music Data Mining.
IEEE Access, 2021

2019
IEEE Access Special Section: Cyber-Physical Systems.
IEEE Access, 2019

Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis.
IEEE Access, 2019

Postural Symmetry Evaluation Based on the Analysis of Temporary and Average CoP Displacements Registered During the Follow-Up Posturography.
IEEE Access, 2019

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs.
IEEE Access, 2019

Simulation Comparison of Frequency Estimation Methods Applied for Power Control in Renewable Energy Systems.
Proceedings of the 16th International Conference on Synthesis, 2019

2018
Low Power Synthesis of Finite State Machines - State Assignment Decomposition Algorithm.
J. Circuits Syst. Comput., 2018

Strategy of logic synthesis using MTBDD dedicated to FPGA.
Integr., 2018

Influence of Noise on Multifrequency Signals for the Amplitude and Phase Estimation in Photovoltaic Systems with a DSP Processor.
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

2017
Logic synthesis for FPGAs based on cutting of BDD.
Microprocess. Microsystems, 2017

Area-oriented technology mapping for LUT-based logic blocks.
Int. J. Appl. Math. Comput. Sci., 2017

Estimation methods of multifrequency signals with noise and harmonics for PV systems with a DSP processor.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

2016
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers.
ACM Trans. Design Autom. Electr. Syst., 2016

Interpolated-DFT-Based Fast and Accurate Amplitude and Phase Estimation for the Control of Power.
CoRR, 2016

2015
Logic Decomposition for PAL-Based CPLDs.
J. Circuits Syst. Comput., 2015

2014
Interpolated-DFT-Based Fast and Accurate Frequency Estimation for the Control of Power.
IEEE Trans. Ind. Electron., 2014

2012
Area and speed oriented synthesis of FSMs for PAL-based CPLDs.
Microprocess. Microsystems, 2012

2010
Logic synthesis based on decomposition for CPLDs.
Microprocess. Microsystems, 2010

Decomposition-based logic synthesis for PAL-based CPLDs.
Int. J. Appl. Math. Comput. Sci., 2010

2009
Synthesis of finite state machines for CPLDs.
Int. J. Appl. Math. Comput. Sci., 2009

State assignment and logic optimization for finite state machines.
Proceedings of the 9th IFAC Workshop on Programmable Devices and Embedded Systems, 2009

CPLD-oriented Synthesis of Finite State Machines.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2007
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition.
J. Syst. Softw., 2007

A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2005
Decomposition of Multi-Output Functions for CPLDs.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

State Assignment for PAL-based CPLDs.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2002
Logic synthesis of multi-output functions for PAL-based CPLDs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions.
Proceedings of the 2002 Design, 2002

2000
A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition.
Proceedings of the 25th EUROMICRO '99 Conference, 1999


  Loading...