Darsh Asher

According to our database, Darsh Asher authored at least 5 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

FeatureBleed: Inferring Private Enriched Attributes From Sparsity-Optimized AI Accelerators.

Darsh Asher, Farshad Dizani, Joshua Kalyanapu, Rosario Cammarota, Aydin Aysu, Samira Mirbagher Ajorpaz

IEEE Comput. Archit. Lett., 2026

2025

GATEBLEED: Exploiting On-Core Accelerator Power Gating for High Performance & Stealthy Attacks on AI.

Joshua Kalyanapu, Farshad Dizani, Darsh Asher, Azam Ghanbari, Rosario Cammarota, Aydin Aysu, Samira Mirbagher Ajorpaz

CoRR, July, 2025

Exploiting Intel AMX Power Gating.

Joshua Kalyanapu, Farshad Dizani, Azam Ghanbari, Darsh Asher, Samira Mirbagher Ajorpaz

IEEE Comput. Archit. Lett., 2025

Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX.

Farshad Dizani, Azam Ghanbari, Joshua Kalyanapu, Darsh Asher, Samira Mirbagher Ajorpaz

IEEE Comput. Archit. Lett., 2025

GateBleed: Exploiting On-Core Accelerator Power Gating for High Performance and Stealthy Attacks on AI.

Joshua Kalyanapu, Farshad Dizani, Darsh Asher, Azam Ghanbari, Rosario Cammarota, Aydin Aysu, Samira Mirbagher Ajorpaz

Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025