Samira Mirbagher Ajorpaz

Orcid: 0009-0008-4997-5980

According to our database1, Samira Mirbagher Ajorpaz authored at least 14 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
FeatureBleed: Inferring Private Enriched Attributes From Sparsity-Optimized AI Accelerators.
IEEE Comput. Archit. Lett., 2026

CacheMind: From Miss Rates to Why - Natural-Language, Trace-Grounded Reasoning for Cache Replacement.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

2025
GATEBLEED: Exploiting On-Core Accelerator Power Gating for High Performance & Stealthy Attacks on AI.
CoRR, July, 2025

Exploiting Intel AMX Power Gating.
IEEE Comput. Archit. Lett., 2025

Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX.
IEEE Comput. Archit. Lett., 2025

GateBleed: Exploiting On-Core Accelerator Power Gating for High Performance and Stealthy Attacks on AI.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2023
An Attack on The Speculative Vectorization: Leakage from Higher Dimensional Speculation.
CoRR, 2023

2022
Dynamic Set Stealing to Improve Cache Performance.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Composite Instruction Prefetching.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2020
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CHiRP: Control-Flow History Reuse Prediction.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Bit-level perceptron prediction for indirect branches.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018


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