Darshika G. Perera

Orcid: 0000-0001-9106-4381

According to our database1, Darshika G. Perera authored at least 33 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Composing Efficient Computational Models for Real-Time Processing on Next-Generation Edge-Computing Platforms.
IEEE Access, 2024

2023
An Effective Content Based Image Retrieval System Using Deep Learning Based Inception Model.
Wirel. Pers. Commun., November, 2023

Land Cover Classification Using Landsat 7 Data for Land Sustainability.
Wirel. Pers. Commun., September, 2023

Neuromorphic Sentiment Analysis Using Spiking Neural Networks.
Sensors, September, 2023

Toward Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based Model Predictive Control Smart Sensor for HEV Battery Cell Management.
IEEE Access, 2023

A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based Hardware Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Edge Computing-based Adaptive Machine Learning Model for Dynamic IoT Environment.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Composing Optimized Embedded Software Architectures for Physics-Based EKF-MPC Smart Sensor for Li-Ion Battery Cell Management.
Sensors, 2022

2021
Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

2020
Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs.
IEEE Access, 2020

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices.
IEEE Access, 2020

An Optimized FPGA-Based Hardware Accelerator for Physics-Based EKF for Battery Cell Management.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Quad Joint Relational Feature for 3D Skeletal Action Recognition with Circular CNNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis.
Microprocess. Microsystems, 2019

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware.
Int. J. Embed. Syst., 2019

A Fast and Secure Pipelined Barrel Processor for Safety-Critical Applications for Real-Time Operating Systems.
Proceedings of the 10th IEEE Annual Ubiquitous Computing, 2019

Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

2018
Efficient embedded architectures for fast-charge model predictive controller for battery cell management in electric vehicles.
EURASIP J. Embed. Syst., 2018

Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017
Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices.
EURASIP J. Embed. Syst., 2017

An efficient FPGA-based memory architecture for compute-intensive applications on embedded devices.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

A fast and scalable FPGA-based parallel processing architecture for K-means clustering for big data analysis.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

An efficient embedded multi-ported memory architecture for next-generation FPGAs.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2015
Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications.
Proceedings of the 12th FPGAworld Conference 2015, 2015

Analysis of Computational Models and Application Characteristics Suitable for Reconfigurable FPGAs.
Proceedings of the 10th International Conference on P2P, 2015

2013
A Hardware Collective Intelligence Agent.
Trans. Comput. Collect. Intell., 2013

2011
FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications.
Proceedings of the 2011 International Conference on P2P, 2011

2009
Similarity Computation Using Reconfigurable Embedded Hardware.
Proceedings of the Eighth IEEE International Conference on Dependable, 2009

2008
Parallel Computation of Similarity Measures Using an FPGA-Based Processor Array.
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008

2007
An Investigation of Chip-Level Hardware Support for Web Mining.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007


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