David Dice

According to our database1, David Dice
  • authored at least 40 papers between 2001 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2017
Towards an Efficient Pauseless Java GC with Selective HTM-Based Access Barriers.
Proceedings of the 14th International Conference on Managed Languages and Runtimes, 2017

Malthusian Locks.
Proceedings of the Twelfth European Conference on Computer Systems, 2017

2016
Dekker's mutual exclusion algorithm made RW-safe.
Concurrency and Computation: Practice and Experience, 2016

Refined transactional lock elision.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Transactional Pointers: Experiences with HTM-Based Reference Counting in C++.
Proceedings of the Networked Systems - 4th International Conference, 2016

Fast non-intrusive memory reclamation for highly-concurrent data structures.
Proceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management, Santa Barbara, CA, USA, June 14, 2016

2015
Lock Cohorting: A General Technique for Designing NUMA Locks.
TOPC, 2015

Malthusian Locks.
CoRR, 2015

The Influence of Malloc Placement on TSX Hardware Transactional Memory.
CoRR, 2015

High-performance N-thread software solutions for mutual exclusion.
Concurrency and Computation: Practice and Experience, 2015

Evaluating HTM for Pauseless Garbage Collectors in Java.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

The TURBO Diaries: Application-controlled Frequency Scaling Explained.
Proceedings of the Software Engineering & Management 2015, Multikonferenz der GI-Fachbereiche Softwaretechnik (SWT) und Wirtschaftsinformatik (WI), FA WI-MAW, 17. März, 2015

2014
Hardware extensions to make lazy subscription safe.
CoRR, 2014

Software-based contention management for efficient compare-and-swap operations.
Concurrency and Computation: Practice and Experience, 2014

The TURBO Diaries: Application-controlled Frequency Scaling Explained.
Proceedings of the 2014 USENIX Annual Technical Conference, 2014

Brief announcement: persistent unfairness arising from cache residency imbalance.
Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures, 2014

Adaptive integration of hardware and software lock elision techniques.
Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures, 2014

2013
Lightweight Contention Management for Efficient Compare-and-Swap Operations
CoRR, 2013

Scalable statistics counters.
Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, 2013

Scalable statistics counters.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Using hardware transactional memory to correct and simplify and readers-writer lock algorithm.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

NUMA-aware reader-writer locks.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Message Passing or Shared Memory: Evaluating the Delegation Abstraction for Multicores.
Proceedings of the Principles of Distributed Systems - 17th International Conference, 2013

Lightweight Contention Management for Efficient Compare-and-Swap Operations.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

2012
Lock cohorting: a general technique for designing NUMA locks.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011
Brief announcement: multilane - a concurrent blocking multiset.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Flat-combining NUMA locks.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Brief announcement: a partitioned ticket lock.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Cache index-aware memory allocation.
Proceedings of the 10th International Symposium on Memory Management, 2011

2010
TLRW: return of the read-write lock.
Proceedings of the SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2010

Simplifying concurrent algorithms by exploiting hardware transactional memory.
Proceedings of the SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2010

Efficient Lock Free Privatization.
Proceedings of the Principles of Distributed Systems - 14th International Conference, 2010

Transactional Mutex Locks.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009
Early experience with a commercial hardware transactional memory implementation.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2007
Potential show-stoppers for transactional synchronization.
Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

Understanding Tradeoffs in Software Transactional Memory.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006
Transactional Locking II.
Proceedings of the Distributed Computing, 20th International Symposium, 2006

2005
Supporting per-processor local-allocation buffers using lightweight user-level preemption notification.
Proceedings of the 1st International Conference on Virtual Execution Environments, 2005

2002
Mostly lock-free malloc.
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002

2001
Implementing Fast Java Monitors with Relaxed-Locks.
Proceedings of the 1st Java Virtual Machine Research and Technology Symposium, 2001


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