Stephan Diestelhorst

According to our database1, Stephan Diestelhorst
  • authored at least 18 papers between 2010 and 2018.
  • has a "Dijkstra number"2 of three.

Timeline

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Links

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Bibliography

2018
SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads.
TACO, 2018

2017
Nucleus: Finding the Sharing Limit of Heterogeneous Cores.
ACM Trans. Embedded Comput. Syst., 2017

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Empirical CPU power modelling and estimation in the gem5 simulator.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Composing lifetime enhancing techniques for non-volatile main memories.
Proceedings of the International Symposium on Memory Systems, 2017

dist-gem5: Distributed simulation of computer clusters.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Language-level persistency.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016
Exploring system performance using elastic traces: Fast, accurate and portable.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Thermally-aware composite run-time CPU power models.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Delegated persist ordering.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Elastic traces for fast and accurate system performance exploration.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015
The TURBO Diaries: Application-controlled Frequency Scaling Explained.
Proceedings of the Software Engineering & Management 2015, Multikonferenz der GI-Fachbereiche Softwaretechnik (SWT) und Wirtschaftsinformatik (WI), FA WI-MAW, 17. März, 2015

2014
The TURBO Diaries: Application-controlled Frequency Scaling Explained.
Proceedings of the 2014 USENIX Annual Technical Conference, 2014

2013
Brief announcement: between all and nothing - versatile aborts in hardware transactional memory.
Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, 2013

2012
Delegation and nesting in best-effort hardware transactional memory.
Proceedings of the 24th ACM Symposium on Parallelism in Algorithms and Architectures, 2012

2010
The Velox Transactional Memory Stack.
IEEE Micro, 2010

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack.
Proceedings of the European Conference on Computer Systems, 2010


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