David Tarjan

According to our database1, David Tarjan authored at least 19 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Dynamic Memory Compression: Retrofitting LLMs for Accelerated Inference.
CoRR, 2024

2018
SDCNet: Video Prediction Using Spatially-Displaced Convolution.
CoRR, 2018

SDC-Net: Video Prediction Using Spatially-Displaced Convolution.
Proceedings of the Computer Vision - ECCV 2018, 2018

2014
Rhythm: harnessing data parallel hardware for server workloads.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2012
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors.
ACM Trans. Comput. Syst., 2012

2011
Energy-efficient mechanisms for managing thread context in throughput processors.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
Federation: Boosting per-thread performance of throughput-oriented manycore architectures.
ACM Trans. Archit. Code Optim., 2010

The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches.
Proceedings of the Conference on High Performance Computing Networking, 2010

Dynamic warp subdivision for integrated branch and memory divergence tolerance.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Increasing memory miss tolerance for SIMD cores.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Accelerating leukocyte tracking using CUDA: A case study in leveraging manycore coprocessors.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Rodinia: A benchmark suite for heterogeneous computing.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

2008
A performance study of general-purpose applications on graphics processors using CUDA.
J. Parallel Distributed Comput., 2008

Federation: repurposing scalar cores for out-of-order instruction issue.
Proceedings of the 45th Design Automation Conference, 2008

2007
Impact of process variations on multicore performance symmetry.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
Merging path and gshare indexing in perceptron branch prediction.
ACM Trans. Archit. Code Optim., 2005

2004
Temperature-aware microarchitecture: Modeling and implementation.
ACM Trans. Archit. Code Optim., 2004

2003
Temperature-Aware Computer Systems: Opportunities and Challenges.
IEEE Micro, 2003

Temperature-Aware Microarchitecture.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003


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