Mircea R. Stan

Orcid: 0000-0003-0577-9976

Affiliations:
  • University of Virginia, Charlottesville, USA


According to our database1, Mircea R. Stan authored at least 204 papers between 1994 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to power- and temperature-aware design of VLSI circuits and systems".

Timeline

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Bibliography

2024
Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation.
CoRR, 2024

2023
Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Editorial Rolling Out the IEEE TVLSI EDICS.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Editorial New Beginnings for IEEE TVLSI.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Advancing Wireless IoT Sensor Networks With Edge-Powered RFID Devices.
Proceedings of the 14th IEEE Annual Ubiquitous Computing, 2023

LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Virtualized Controller for Computational RFID-based IoT Sensors.
Proceedings of the IEEE International Conference on RFID, 2023

ISVABI: In-Storage Video Analytics Engine with Block Interface.
Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, 2023

A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT Nodes.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

FreezeTime: Towards System Emulation through Architectural Virtualization.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

FreezeTime: Towards System Emulation through Architectural Virtualization.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Hardware Trojans in eNVM Neuromorphic Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Thermal Performance Analysis of Mempool RISC-V Multicore SoC.
IEEE Trans. Very Large Scale Integr. Syst., 2022

EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT.
Sustain. Comput. Informatics Syst., 2022

Agile-AES: Implementation of configurable AES primitive with agile design approach.
Integr., 2022

Scheduling Active and Accelerated Recovery to Combat Aging in Integrated Circuits.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

ISKEVA: in-SSD key-value database engine for video analytics applications.
Proceedings of the LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, 2022

Processing-in-Memory with Temporal Encoding.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Gearbox: a case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge.
Proceedings of the 7th IEEE World Forum on Internet of Things, 2021

Power and Thermal Modeling of In-3D-Memory Computing.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

Microarchitecture Optimization for Asynchronous Stochastic Computing.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams.
ACM J. Emerg. Technol. Comput. Syst., 2020

Temporal Memory with Magnetic Racetracks.
CoRR, 2020

VLSI for Next Generation CE.
IEEE Consumer Electron. Mag., 2020

Memristive Learning Cellular Automata: Theory and Applications.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Nano-Crossbar based Computing: Lessons Learned and Future Directions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
MTTF Enhancement Power-C4 Bump Placement Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Automata Processing in Reconfigurable Architectures: In-the-Cloud Deployment, Cross-Platform Evaluation, and Fast Symbol-Only Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2019

A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing.
IEEE Comput. Archit. Lett., 2019

Error-latency Trade-off for Asynchronous Stochastic Computing with ΣΔ Streams for the IoT.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Asynchronous Stream Computing for Low Power IoT.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

ASC-FFT: Area-Efficient Low-Latency FFT Design Based on Asynchronous Stochastic Computing.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

An Overflow-free Quantized Memory Hierarchy in General-purpose Processors.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Towards low-power random forest using asynchronous computing with streams.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Fourier-based Error Analysis for Computing with Asynchronous Sigma-Delta Streams.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

Asynchronous Stochastic Computing.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Hardware based Spatio-Temporal Neural Processing Backend for Imaging Sensors: Towards a Smart Camera.
CoRR, 2018

MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem.
IEEE Comput. Archit. Lett., 2018

Co-Optimizing CPUs and Accelerators in Constrained Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Integrated Synthesis Methodology for Crossbar Arrays.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

When "things" get older: Exploring circuit aging in IoT applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

AutomataZoo: A Modern Automata Processing Benchmark Suite.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Reservoir Computing Based Neural Image Filters.
Proceedings of the IECON 2018, 2018

SC-SD: Towards Low Power Stochastic Computing Using Sigma Delta Streams.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration.
Proceedings of the 55th Annual Design Automation Conference, 2018

SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.
J. Signal Process. Syst., 2017

Hierarchical Temporal Memory on the Automata Processor.
IEEE Micro, 2017

Back to the Future: Digital Circuit Design in the FinFET Era.
J. Low Power Electron., 2017

Implications of accelerated self-healing as a key design knob for cross-layer resilience.
Integr., 2017

Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade?
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017


REAPR: Reconfigurable engine for automata processing.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Near-Memory Data Services.
IEEE Micro, 2016

Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Attacking an SRAM-Based PUF through Wearout.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Generating efficient and high-quality pseudo-random behavior on Automata Processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

An overview of micron's automata processor.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Association Rule Mining with the Micron Automata Processor.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Architecture implications of pads as a scarce resource.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Computing with Hybrid CMOS/STO Circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Walking pads: Fast power-supply pad-placement optimization.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Modeling Power Consumption of NAND Flash Memories Using FlashPower.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Architectural implications of spatial thermal filtering.
Integr., 2013

Nano-pattemed coupled spin torque nano oscillator (STNO) arrays - A potentially disruptive multipurpose nanotechnology.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Breaking power delivery walls using voltage stacking.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012
Tracking On-Chip Age Using Distributed, Embedded Sensors.
IEEE Trans. Very Large Scale Integr. Syst., 2012

ArchFP: Rapid prototyping of pre-RTL floorplans.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Design of near threshold All Digital Delay Locked Loops.
Proceedings of the IEEE 25th International SOC Conference, 2012

Self-assembled multiferroic magnetic QCA structures for low power systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A new taxonomy for reconfigurable prefix adders.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Breaking the power delivery wall using voltage stacking.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Breaking the 3D IC power delivery wall.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Thermal benefit of multi-core floorplanning: A limits study.
Sustain. Comput. Informatics Syst., 2011

Scaling with Design Constraints: Predicting the Future of Big Chips.
IEEE Micro, 2011

Temperature-Aware Architecture: Lessons and Opportunities.
IEEE Micro, 2011

Modeling and analyzing NBTI in the presence of Process Variation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM).
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

The STeTSiMS STT-RAM simulation and modeling system.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Relaxing non-volatility for fast and energy-efficient STT-RAM caches.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

RAMA: a self-assembled multiferroic magnetic QCA for low power systems.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory.
Proc. IEEE, 2010

Temperature-to-power mapping.
Proceedings of the 28th International Conference on Computer Design, 2010

How I Learned to Stop Worrying and Love Flash Endurance.
Proceedings of the 2nd USENIX Workshop on Hot Topics in Storage and File Systems, 2010

Reliability/wearout-aware design.
Proceedings of the International Green Computing Conference 2010, 2010

FlashPower: A detailed power model for NAND flash memory.
Proceedings of the Design, Automation and Test in Europe, 2010

SRAM-based NBTI/PBTI sensor system design.
Proceedings of the 47th Design Automation Conference, 2010

Stacking SRAM banks for ultra low power standby mode operation.
Proceedings of the 47th Design Automation Conference, 2010

Improving SRAM Vmin and yield by using variation-aware BTI stress.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Sensitivity-Based Optimization of Disk Architecture.
IEEE Trans. Computers, 2009

Using Intradisk Parallelism to Build Energy-Efficient Storage Systems.
IEEE Micro, 2009

Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Differentiating the roles of IR measurement and simulation for power and temperature-aware design.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

Graphene Devices, Interconnect and Circuits - Challenges and Opportunities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Electromigration-aware design.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model.
IEEE Trans. Computers, 2008

Sensitivity Based Power Management of Enterprise Storage Systems.
Proceedings of the 16th International Symposium on Modeling, 2008

Intra-disk Parallelism: An Idea Whose Time Has Come.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

NBTI resilient circuits using adaptive body biasing.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Many-core design from a thermal perspective.
Proceedings of the 45th Design Automation Conference, 2008

2007
Interconnect Lifetime Prediction for Reliability-Aware Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Programmable Majority Logic Array Using Molecular Scale Electronics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Conformational Molecular Switches for Post-CMOS Nanoelectronics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Designing CMOS/molecular memories while considering device parameter variations.
ACM J. Emerg. Technol. Comput. Syst., 2007

Teaching Top-Down ASIC/SoC Design vs Bottom-Up Custom VLSI.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Accurate Back-of-the-Envelope Transistor Model for Deep Sub-micron MOS.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Multi-Dimensional Circuit and Micro-Architecture Level Optimization.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Structured and tuned array generation (STAG) for high-performance random logic.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Temperature-aware circuit design using adaptive body biasing.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

SODA: Sensitivity Based Optimization of Disk Architecture.
Proceedings of the 44th Design Automation Conference, 2007

2006
HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Hybrid CMOS/Molecular Electronic Circuits.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Design approaches for hybrid CMOS/molecular memory based on experimental device data.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Procrastinating voltage scheduling with discrete frequency sets.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Improved Thermal Management with Reliability Banking.
IEEE Micro, 2005

A Case for Thermal-Aware Floorplanning at the Microarchitectural Level.
J. Instr. Level Parallelism, 2005

The need for a full-chip and package thermal model for thermally optimized IC designs.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A three-level toggle-avoid bus signaling scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Monitoring Temperature in FPGA based SoCs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Optimal procrastinating voltage scheduling for hard real-time systems.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Large-signal two-terminal device model for nanoelectronic circuit analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Power-Aware Branch Prediction: Characterization and Design.
IEEE Trans. Computers, 2004

Temperature-aware microarchitecture: Modeling and implementation.
ACM Trans. Archit. Code Optim., 2004

Non-Manhattan maze routing.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Perfect 3-Limited-Weight Code for Low Power I/O.
Proceedings of the Integrated Circuit and System Design, 2004

Systolic counters with unique zero state.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Interconnect lifetime prediction under dynamic stress for reliability-aware design.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A Unified Design Space for Regular Parallel Prefix Adders.
Proceedings of the 2004 Design, 2004

State-Preserving vs. Non-State-Preserving Leakage Control in Caches.
Proceedings of the 2004 Design, 2004

Compact thermal modeling for temperature-aware design.
Proceedings of the 41th Design Automation Conference, 2004

System level leakage reduction considering the interdependence of temperature and leakage.
Proceedings of the 41th Design Automation Conference, 2004

2003
Molecular electronics: from devices and interconnect to circuits and architecture.
Proc. IEEE, 2003

HotSpot: a dynamic compact thermal model at the processor-architecture level.
Microelectron. J., 2003

Temperature-Aware Computer Systems: Opportunities and Challenges.
IEEE Micro, 2003

Alloyed Branch History: Combining Global and Local Branch History for Robust Performance.
Int. J. Parallel Program., 2003

Guest Editors' Introduction: Power-Aware Computing.
Computer, 2003

The CMOS/nano interface from a circuits perspective.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

MTCMOS with outer feedback (MTOF) flip-flops.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Temperature-Aware Microarchitecture.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Reducing Multimedia Decode Power using Feedback Control.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Analysis of dual-V<sub>T</sub> SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. Very Large Scale Integr. Syst., 2002

5-GHz 32-bit integer execution core in 130-nm dual-V<sub>T</sub> CMOS.
IEEE J. Solid State Circuits, 2002

CMOS Circuits with Subvolt Supply Voltages.
IEEE Des. Test Comput., 2002

Teaching processor architecture with a VLSI perspective.
Proceedings of the 2002 workshop on Computer architecture education, 2002

Odd/even bus invert with two-phase transfer for buses with coupling.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Circuit-level techniques to control gate leakage for sub-100nm CMOS.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A Case for CMOS/nano co-design.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Power Issues Related to Branch Prediction.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits.
Proceedings of the 2002 Design, 2002

Control-theoretic dynamic frequency and voltage scaling for multimedia workloads.
Proceedings of the International Conference on Compilers, 2002

2001
Low Power Design for ASIC Cores.
VLSI Design, 2001

Low-power CMOS with subvolt supply voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Active threshold compensation circuit for improved performance in cooled CMOS systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Limits to Voltage Scaling from the Low Power Perspective.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999
Optimal Voltages and Sizing for Low Power.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Challenges in clockgating for a low power ASIC methodology.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1998
Long and Fast Up/Down Counters.
IEEE Trans. Computers, 1998

Low threshold CMOS circuits with low standby current.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Low power architecture of the soft-output Viterbi algorithm.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Low-power encodings for global communication in CMOS VLSI.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Power reduction techniques for a spread spectrum based correlator.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Synchronous Up/Down Counter with Clock Period Independent of Counter Size.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996
Two dimensional codes for low power.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Bus-invert coding for low-power I/O.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Coding a terminated bus for low power.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
Analog VLSI for robot path planning.
J. VLSI Signal Process., 1994


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