Daniel R. Johnson

According to our database1, Daniel R. Johnson authored at least 18 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
GPU Subwarp Interleaving.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2020
Speculative reconvergence for improved SIMT efficiency.
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020

2017
Architecting an Energy-Efficient DRAM System for GPUs.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
A patch memory system for image processing and computer vision.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
Flexible software profiling of GPU architectures.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A variable warp size architecture.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Priority-based cache allocation in throughput processors.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Scaling the Power Wall: A Path to Exascale.
Proceedings of the International Conference for High Performance Computing, 2014

2012
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors.
ACM Trans. Comput. Syst., 2012

2011
Cohesion: An Adaptive Hybrid Memory Model for Accelerators.
IEEE Micro, 2011

Rigel: A 1, 024-Core Single-Chip Accelerator Architecture.
IEEE Micro, 2011

Energy-efficient mechanisms for managing thread context in throughput processors.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
A Task-Centric Memory Model for Scalable Accelerator Architectures.
IEEE Micro, 2010

Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture.
Proceedings of the Computer Architecture, 2010

Cohesion: a hybrid memory model for accelerators.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

GoldMine: Automatic assertion generation using data mining and static analysis.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Rigel: an architecture and scalable programming interface for a 1000-core accelerator.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008
Tradeoffs in designing accelerator architectures for visual computing.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008


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